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SSM2018P-SSM2018TPZ
Trimless Voltage Controlled Amplifier
FUNCTIONAL BLOCK DIAGRAM
FEATURES
117dB Dynamic Range
0.006% Typical THD+N (@ 1 kHz, Unity Gain)
140dB Gain Range
No External Trimming Required
Differential Inputs
Complementary Gain Outputs
Buffered Control Port
I–V Converter On-Chip
Low External Parts Count
Low Cost
Trimless
Voltage Controlled AmplifiersREV. B
GENERAL DESCRIPTIONThe SSM2018T represents continuing evolution of the Frey
Operational Voltage Controlled Element (OVCE) topology that
permits flexibility in the design of high performance volume
control systems. The SSM2018T is laser trimmed for gain core
symmetry and offset. As a result, the SSM2018T is the first
professional audio quality VCA to offer trimless operation.
Due to careful gain core layout, the SSM2018T combines the
low noise of Class AB topologies with the low distortion of
Class A circuits to offer an unprecedented level of sonic trans-
parency. Additional features include differential inputs, a 140dB
(–100 dB to +40 dB) gain range and a high impedance control
port. The SSM2018T provides an internal current-to-voltage
converter. Thus no external active components are required.
This device is offered in 16-lead plastic DIP and SOIC packages
and guaranteed for operation over the extended industrial tempera-
ture range of –40∞C to +85∞C.
*. Patent Nos. 4,471,320 and 4,560,947.
SSM2018T–SPECIFICATIONS
ELECTRICAL SPECIFICATIONSINPUT AMPLIFIER
CONTROL PORT
POWER SUPPLIES
Specifications subject to change without notice.
(VS = �15V, AV = 0dB, RL = 100k�, f = 1kHz, 0dBu = 0.775Vrms, simple VCA application
circuit with 18k� resistors, –VIN floating, and Class AB gain core bias (RB = 150k�), –40�C < TA < +85�C, unless otherwise noted. Typical
specifications apply at TA = 25�C.)
ABSOLUTE MAXIMUM RATINGS1Supply Voltage
Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Operating Temperature Range . . . . . . . . . . . .–40∞C to +85∞C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65∞C to +150∞C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . .150∞C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . .300∞C
THERMAL CHARACTERISTICSThermal Resistance2
16-Lead Plastic DIP
�JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76∞C/W
�JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33∞C/W
16-Lead SOIC
�JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92∞C/W
�JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27∞C/W
TRANSISTOR COUNTNumber of Transistors
SSM2018T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
ESD RATINGS883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . .500V
EIAJ Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100V
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operation
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2�JA is specified for worst-case conditions, i.e.; �JA is specified for device in socket for
P-DIP and device soldered in circuit board for SOIC package.
PIN CONFIGURATION
16-Lead Plastic DIP
and SOL
ORDERING GUIDEN = Plastic DIP; R = SOL.Not for new designs; obsolete April 2002.
SSM2018T Typical Application Circuit
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SSM2018T features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precau-
tions are recommended to avoid performance degradation or loss of functionality.
SSM2018T–Typical Performance CharacteristicsTPC 1.SSM2018T THD + N Frequency (80 kHz Low-Pass
Filter, for AV = 0 dB, VIN = 3 V rms; for AV = +20 dB,
VIN = 0.3 V rms; for AV = –20 dB, VIN = 3 V rms)
TPC 2.SSM2018T Distortion Distribution
TPC 4.SSM2018T THD + N vs. Amplitude
(Gain = +20 dB, fIN=1 kHz, 80 kHz Low-Pass Filter)
TPC 5.SSM2018T THD + N vs. Gain (fIN = 1 kHz;
for –60 dB £ AV £ –20 dB, VIN = 10 V rms;
for 0 dB £ AV £ +20 dB, VIN = 1 V rms)
TPC 7.SSM2018T Noise Density vs. Frequency
(Unity Gain, Referred to Input)
TPC 8.SSM2018T Maximum Output Swing vs.
Supply Voltage (THD = 1% max)
TPC 9.SSM2018T Maximum Output Swing vs.
Frequency (THD = 1 % max)
TPC 10.SSM2018T Maximum Output Swing vs.
Load Resistance (THD = 1 % max)
TPC 11.SSM2018T Typical Output Offset vs. Gain
TPC 12.SSM2018T Gain/Phase vs. Frequency
SSM2018TTPC 16.SSM2018T Control Feedthrough Distribution
Figure 17.SSM2018T Control Feedthrough vs. Frequency
TPC 18.SSM2018T Control Feedthrough vs.
Temperature
TPC 19.SSM2018T Gain Constant vs. Temperature
TPC 20.SSM2018T Gain Constant Linearity vs. Gain
TPC 21.SSM2018T Gain Flatness vs. Frequency
TPC 22.SSM2018T CMRR vs. Frequency
TPC 23.SSM2018T Slew Rate vs. Supply Voltage
TPC 24.SSM2018T PSRR vs. Frequency
SSM2018Tnormal and actually disables that output amplifier ensuring that
it will not oscillate and cause interference problems. Shorting
the output to the negative supply does not cause the supply
current to increase. This amplifier is only used in the “OVCE”
application explained later.
The control port follows a –30 mV/dB control law. The applica-
tion circuit shows a 3 kW and 1 kW resistor divider from a control
voltage. The choice of these resistors is arbitrary and could be
any values to properly scale the control voltage. In fact, these
resistors can be omitted if the control voltage has been properly
scaled. The 1 mF capacitor is in place to provide some filtering
of the control signal. Although the control feedthrough is trimmed
at the factory, the feedthrough increases with frequency (TPC
16). Thus, high frequency noise can feed through and add to
the noise of the VCA. Filtering the control signal helps minimize
this noise source.
Theory of Operation of the SSM2018TThe SSM2018T has the same internal circuitry as the original
SSM2018. The detailed diagram in Figure 2 shows the main
components of the VCA. The essence of the SSM2018T is
the gain core, which comprises two differential pairs (Q1–Q4).
When the control voltage, VC, is adjusted, current through the
gain core is steered to one side or the other of the two differential
pairs. The tail current for these differential pairs is set by the
mode bias of the VCA (Class A or AB), which is labeled as IM in
the diagram. IM is then modulated by a current proportional to
the input voltage, labeled IS. For a positive input voltage, more
current is steered (by the “Splitter”) to the left differential pair;
the opposite is true for a negative input.
To understand how the gain control works, a simple example is
best. Take the case of a positive control voltage on Pin 11. Notice
that the bases of Q2 and Q3 are connected to ground via a 200W resistor. A positive control voltage produces a positive voltage
on the bases of Q1 and Q4. Concentrating on the left-most
differential pair, this raises the base voltage of Q1 above that of
Q2. Thus, more of the tail current is steered through Q1 than
through Q2. The current from the collector of Q2 flows through
the external 18 kW feedback resistor around amplifier A3. When
this current is reduced, the output voltage is also reduced. Thus,
a positive control voltage results in an attenuation of the input
signal, which explains why the gain constant is negative.
The collector currents of Q2 and Q3 produce the output voltage.
The output of Q3 is mirrored by amplifier A1 to add to the
overall output voltage. On the other hand, the collector currents
of Q1 and Q4 are used for feedback to the differential inputs.
Because Pins 6 and 4 are shorted together, any input voltage
produces an input current which flows into Pin 4. The same is
true for the inverting input, which is connected to Pin 1. The
overall feedback ensures that the current flowing through the
input resistors is balanced by the collector currents in Q1 and Q4.
Compensating the SSM2018TThe SSM108 has a network that uses an adaptive compensation
scheme that adjusts the optimum compensation level for a given
gain. The control voltage not only adjusts the gain core steering,
it also adjusts the compensation. The SSM2018T has three
compensation pins: COMP1, COMP2, and COMP3. COMP3
APPLICATIONSThe SSM2018T is a trimless Voltage Controlled Amplifier (VCA)
for volume control in audio systems. The SSM2018T is identi-
cal to the original SSM2018 in functionality and pinout; how-
ever, it is the first professional quality audio VCA in the
marketplace that does not require an external trimming potenti-
ometer to minimize distortion. Instead, the SSM2018T is laser
trimmed before it is packaged to ensure the specified THD and
control feedthrough performance. This has a significant savings
in not only the cost of external trimming potentiometers, but
also the manufacturing cost of performing the trimming during
production.
Basic VCA ConfigurationThe primary application circuit for the SSM2018T is the basic
VCA configuration, which is shown in Figure 1. This configura-
tion uses differential current feedback to realize the VCA. A
complete description of the internal circuitry of the VCA, and
this configuration, is given in the Theory of Operation section
below. The SSM2018T is trimmed at the factory for operation in the
basic VCA configuration with class AB biasing. Thus, for optimal
distortion and control feedthrough performance, the same con-
figuration and biasing should be used. All of the graphs for the
SSM2018T in the data sheet have been measured using the
circuit of Figure 1.
Figure 1.Basic VCA Application Circuit
In the simple VCA configuration, the SSM2018T inputs are at a
virtual ground. Thus, 18 kW resistors are required to convert the
input voltages to input currents. The schematic also shows ac
coupling capacitors. These are inserted to minimize dc offsets
generated by bias current through the resistors. Without the
capacitors, the dc offset due to the input bias current is typically
5 mV. The input stage has the flexibility to run either inverting,
noninverting, or balanced. The most common configuration is
to run it in the noninverting single-ended mode. If either input
is unused, the associated 18 kW resistor and coupling capacitor
should be removed to prevent any additional noise.
The common-mode rejection in balanced mode is typically
55 dB up to 1 kHz, decreasing at higher frequencies as shown in
TPC 21. To ensure good CMRR in the balanced configuration,
the input resistors must be balanced. For example, a 1% mis-
match results in a CMRR of 40 dB. To achieve 55 dB, these
resistors should have an absolute tolerance match of 0.1%.
