SPC560B40L3 ,32-bit Power Architecture MCU for Automotive Body and Gateway ApplicationsFeatures ■ High-performance 64 MHz e200z0h CPU®– 32-bit Power Architecture technologyLQFP100 (14 x ..
SPC560P40L3CEFAR ,32-bit Power Architecture MCU for Automotive Chassis and Safety ApplicationsFeatures■ Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h)®– Compliant with Power Arch ..
SPC560P50L3 ,32-bit Power Architecture MCU for Automotive Chassis and Safety ApplicationsFeatures■ 64 MHz, single issue, 32-bit CPU core complex (e200z0h)®– Compliant with Power Architectu ..
SPC563M64L5COAR ,32-bit Power Architecture MCU for Automotive Powertrain ApplicationsFeatures20 mm x 20 mm 14 mm x 14 mm®■ Single issue, 32-bit Power Architecture Book E compliant e200 ..
SPC563M64L5COAY ,32-bit Power Architecture MCU for Automotive Powertrain Applicationselectrical characteristics . 1024.15 AC specifications . . 1044.15.1 Pad AC specifications ..
SPC5673FF3MVR3 , MPC5674F Microcontroller Data Sheet
SST39VF040-70-4C-WH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-70-4C-WH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-70-4I-WH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-90-4C-NH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-90-4C-NH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-90-4C-WH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SPC560B40L3
32-bit Power Architecture MCU for Automotive Body and Gateway Applications
September 2013 Doc ID 14619 Rev 12 1/117
SPC560B40x, SPC560B50x
SPC560C40x, SPC560C50x32-bit MCU family built on the Power Architecture®
for automotive body electronics applications
Datasheet − production data
Features High-performance 64 MHz e200z0h CPU 32-bit Power Architecture® technology Up to 60 DMIPs operation Variable length encoding (VLE) Memory Up to 512 KB Code Flash with ECC 64 KB Data Flash with ECC Up to 48 KB SRAM with ECC 8-entry memory protection unit (MPU) Interrupts 16 priority levels Non-maskable interrupt (NMI) Up to 34 external interrupts incl. 18 wakeup
lines GPIO: 45(LQFP64), 75(LQFP100),
123(LQFP144) Timer units 6-channel 32-bit periodic interrupt timers 4-channel 32-bit system timer module Software watchdog timer Real-time clock timer 16-bit counter time-triggered I/Os Up to 56 channels with PWM/MC/IC/OC ADC diagnostic via CTU Communications interface Up to 6 FlexCAN interfaces (2.0B active)
with 64-message objects each Up to 4 LINFlex/UART 3 DSPI / I2C Single 5 V or 3.3 V supply 10-bit analog-to-digital converter (ADC) with up
to 36 channels Extendable to 64 channels via external
multiplexing Individual conversion registers Cross triggering unit (CTU) Dedicated diagnostic module for lighting Advanced PWM generation Time-triggered diagnostic PWM-synchronized ADC measurements Clock generation 4 to 16 MHz fast external crystal oscillator
(FXOSC) 32 kHz slow external crystal oscillator
(SXOSC) 16 MHz fast internal RC oscillator (FIRC) 128 kHz slow internal RC oscillator (SIRC) Software-controlled FMPLL Clock monitor unit (CMU) Exhaustive debugging capability Nexus1 on all devices Nexus2+ available on emulation package
(LBGA208) Low power capabilities Ultra-low power standby with RTC, SRAM
and CAN monitoring Fast wakeup schemes Operating temp. range up to -40 to 125 °C
Table 1. Device summary All LQFP64information is indicative and must be confirmed during silicon validation.
Contents SPC560B40x/50x, SPC560C40x/50x2/117 Doc ID 14619 Rev 12
Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 143.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.10 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.11 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.11.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.11.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 39
3.11.3 NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 39
3.12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.13 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.14 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.14.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.14.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.15 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.15.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.15.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.15.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.15.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.15.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPC560B40x/50x, SPC560C40x/50x ContentsDoc ID 14619 Rev 12 3/117
3.16 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.17 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 60
3.17.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 60
3.17.2 Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . 66
3.18 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.19 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.19.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.19.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.19.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.20 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 71
3.20.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 71
3.20.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.20.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 72
3.21 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 73
3.22 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 76
3.23 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.24 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 80
3.25 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 81
3.26 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.26.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.26.3 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.27 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.27.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.27.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.27.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.27.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2.1 LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2.2 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2.3 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.4 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Contents SPC560B40x/50x, SPC560C40x/50x4/117 Doc ID 14619 Rev 12
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SPC560B40x/50x, SPC560C40x/50x List of tablesDoc ID 14619 Rev 12 5/117
List of tablesTable 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. SPC560B40x/50x and SPC560C40x/50x device comparison . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary . . . . . . . . . . . . . . . . . . . . 12
Table 4. Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 11. WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 13. Recommended operating conditions (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 14. Recommended operating conditions (5.0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 15. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 16. I/O input DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 17. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 18. SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 19. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 48
Table 20. FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 21. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 22. I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 23. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 24. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 25. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 26. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 27. Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 28. Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 29. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 30. Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 31. Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 32. Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 33. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 34. EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 36. Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 37. Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 76
Table 39. Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 78
Table 41. FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 80
Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 81
Table 44. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 45. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 46. On-chip peripherals current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 47. DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 48. Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
List of tables SPC560B40x/50x, SPC560C40x/50x6/117 Doc ID 14619 Rev 12
Table 49. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 50. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 51. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 52. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 53. LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 54. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 55. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SPC560B40x/50x, SPC560C40x/50x List of figuresDoc ID 14619 Rev 12 7/117
List of figuresFigure 1. SPC560B40x/50x and SPC560C40x/50x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. LQFP 64-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. LQFP 100-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. LQFP 144-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. LBGA208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 7. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 8. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 9. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 10. VDD_HV and VDD_BV maximum slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 11. VDD_HV and VDD_BV supply constraints during STANDBY mode exit . . . . . . . . . . . . . . . . 63
Figure 12. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 13. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 14. Fast external crystal oscillator (4 to 16 MHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . 75
Figure 15. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 16. Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 17. Slow external crystal oscillator (32 kHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 18. ADC characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 19. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 20. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 21. Transient behavior during sampling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 22. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 23. DSPI classic SPI timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 24. DSPI classic SPI timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 25. DSPI classic SPI timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 26. DSPI classic SPI timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 27. DSPI modified transfer format timing – master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 28. DSPI modified transfer format timing – master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 29. DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 30. DSPI modified transfer format timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 31. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 32. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 33. Timing diagram – JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 34. LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 35. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 36. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 37. LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 38. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Introduction SPC560B40x/50x, SPC560C40x/50x8/117 Doc ID 14619 Rev 12
1 Introduction
1.1 Document overviewThis document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device. To
ensure a complete understanding of the device functionality, refer also to the device
reference manual and errata sheet.
1.2 DescriptionThe SPC560B40x/50x and SPC560C40x/50x is a family of next generation microcontrollers
built on the Power Architecture embedded category.
The SPC560B40x/50x and SPC560C40x/50x family of 32-bit microcontrollers is the latest
achievement in integrated automotive application controllers. It belongs to an expanding
family of automotive-focused products designed to address the next wave of body
electronics applications within the vehicle. The advanced and cost-efficient host processor
core of this automotive controller family complies with the Power Architecture embedded
category and only implements the VLE (variable-length encoding) APU, providing improved
code density. It operates at speeds of up to 64 MHz and offers high performance processing
optimized for low power consumption. It capitalizes on the available development
infrastructure of current Power Architecture devices and is supported with software drivers,
operating systems and configuration code to assist with users implementations.
SPC560B40x/50x, SPC560C40x/50x IntroductionDoc ID 14619 Rev 12 9/117
le 2
60B4
0x/
50x
SP
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Introduction SPC560B40x/50x, SPC560C40x/50x10/117 Doc ID 14619 Rev 12
eat
ure
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ndent
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lect
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ent
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pare;
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Pulse
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tion;
MC
odulus count
SCI
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and
are available.
SCI
is not
av
lable.
CAN0
, CAN1 are availabl
CAN2,
CA
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CA
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CAN1
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s2+
SPC560B40x/50x, SPC560C40x/50x Block diagramDoc ID 14619 Rev 12 11/117
2 Block diagramFigure 1 shows a top-level block diagram of the SPC560B40x/50x and SPC560C40x/50x
device series.
Figure 1. SPC560B40x/50x and SPC560C40x/50x block diagram
Block diagram SPC560B40x/50x, SPC560C40x/50x12/117 Doc ID 14619 Rev 12
Table 3 summarizes the functions of all blocks present in the SPC560B40x/50x and
SPC560C40x/50x series of microcontrollers. Please note that the presence and number of
blocks vary by device and package.
Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary
SPC560B40x/50x, SPC560C40x/50x Block diagram
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Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary (continued)
Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x
14/117 Doc ID 14619 Rev 12 Package pinouts and signal descriptions
3.1 Package pinouts
The available LQFP pinouts and the LBGA208 ballmap are provided in the following figures.
For pin signal descriptions, please refer to the device reference manual (RM0017).
Figure 2. LQFP 64-pin configuration(a)
a.All LQFP64 information is indicative and must be confirmed during silicon validation.
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Figure 3. LQFP 100-pin configuration
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Figure 4. LQFP 144-pin configuration
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Figure 5. LBGA208 configuration
3.2 Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are forced to tristate with the following exceptions: PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from
flash. PA[8] (ABS[0]) is pull-up. RESET pad is driven low. This is pull-up only after PHASE2 reset completion. JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate. Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available). Main oscillator pads (EXTAL, XTAL) are tristate. Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.
1234567 89 10 11 12 13 14 15 16 A B C DE F G H JKL M N P R T
1234567 89 10 11 12 13 14 15 16
Note: LBGA208 available only as development package for Nexus 2+. = Not connected
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3.3 Voltage supply pins
Voltage supply pins are used to provide power to the device. Three dedicated
VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization.
3.4 Pad types
In the device the following types of pads are available for system pins and functional port
pins:
S = Slow(b)
M = Mediumb (c)
F = Fastb c
I = Input only with analog featureb
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator
Table 4. Voltage supply pin descriptions LBGA208 available only as development package for Nexus2+ A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage
(see the recommended operating conditions in the device datasheet for details).
b.See the I/O pad electrical characteristics in the device datasheet for details.
c.All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium
(see PCR.SRC in section Pad Configuration Registers (PCR0–PCR122) in the device reference manual).
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3.5 System pins
The system pins are listed in Table5.
3.6 Functional ports
The functional port pins are listed in Table6
Table 5. System pin descriptions LBGA208 available only as development package for Nexus2+ See the relevant section of the datasheet
Table 6. Functional port pin descriptions
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
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Table 6. Functional port pin descriptions (continued)
Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x
36/117 Doc ID 14619 Rev 12 Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA=00→ AF0;
PCR.PA=01→ AF1; PCR.PA=10→ AF2; PCR.PA=11→ AF3. This is intended to select the output functions; to use
one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields.
For this reason, the value corresponding to an input only function is reported as “—”. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module. LBGA208 available only as development package for Nexus2+ All WKPU pins also support external interrupt capability. See wakeup unit chapter for further details. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. “Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the
reference manual for details. Value of PCR.IBE bit must be 0
Table 6. Functional port pin descriptions (continued)
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3.7 Nexus 2+ pins
In the LBGA208 package, eight additional debug pins are available (see Table7).
3.8 Electrical characteristics
3.9 Introduction
This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid applying any voltage higher
than the specified maximum rated voltages. Be aware that this pad is used on the SPC560B64L3 and SPC560B64L5 to provide VDD_HV_ADC and VSS_HV_ADC1.
Therefore, you should be careful in ensuring compatibility between SPC560B40x/50x and SPC560C40x/50x and
SPC560B64. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1-2001.
10. The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY
mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an
input. When no debugger is connected the TDO pad is floating causing additional current consumption. To avoid the extra
consumption TDO must be connected. An external pull-up resistor in the range of 47–100 kΩ should be added between the
TDO pin and VDD_HV. Only in case the TDO pin is used as application pin and a pull-up cannot be used then a pull-down
resistor with the same value should be used between TDO pin and GND instead.
11. Available only on SPC560Cx versions and SPC560B50B2 devices
12. Not available on SPC560B40L3 and SPC560B40L5 devices
13. Not available in 100 LQFP package
14. Available only on SPC560B50B2 devices
15. Not available on SPC560B44L3 devices
Table 7. Nexus 2+ pin descriptions LBGA208 available only as development package for Nexus2+
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38/117 Doc ID 14619 Rev 12
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS). This could be done by the internal pull-up and pull-down, which is provided by the
product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
Caution:
All LQFP64 information is indicative and must be confirmed during silicon validation.
3.10 Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 8 are used and
the parameters are tagged accordingly in the tables where appropriate.
Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.11 NVUSRO register
Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the
device configuration, namely electrical parameters such as high voltage supply and
oscillator margin, as well as digital functionality (watchdog enable/disable after reset).
For a detailed description of the NVUSRO register, please refer to the device reference
manual.
3.11.1 NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 9 shows
how NVUSRO[PAD3V5V] controls the device configuration.
Table 8. Parameter classifications
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3.11.2 NVUSRO[OSCILLATOR_MARGIN] field description
The fast external crystal oscillator consumption is dependent on the
OSCILLATOR_MARGIN bit value. Table 10 shows how NVUSRO[OSCILLATOR_MARGIN]
controls the device configuration.
3.11.3 NVUSRO[WATCHDOG_EN] field description
The watchdog enable/disable configuration after reset is dependent on the
WATCHDOG_EN bit value. Table 11 shows how NVUSRO[WATCHDOG_EN] controls the
device configuration.
Table 9. PAD3V5V field description Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
Table 10. OSCILLATOR_MARGIN field description Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
Table 11. WATCHDOG_EN field description Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
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3.12 Absolute maximum ratings
Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN >VDD or VIN the voltage on pins with respect to ground (VSS) must not exceed the recommended values.
Table 12. Absolute maximum ratings
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3.13 Recommended operating conditions
Table 13. Recommended operating conditions (3.3V) 100 nF capacitance needs to be provided between each VDD/VSS pair 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 400 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is
reset. Guaranteed by device validation Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH)
Table 14. Recommended operating conditions (5.0V)
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Note: RAM data retention is guaranteed with V DD_LV not below 1.08 V. 100 nF capacitance needs to be provided between each VDD/VSS pair. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog
electrical characteristics will not be guaranteed to stay within the stated limits. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Guaranteed by device validation Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH)
Table 14. Recommended operating conditions (5.0 V) (continued)
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3.14 Thermal characteristics
3.14.1 Package thermal characteristics
Table 15. LQFP thermal characteristics(1) Thermal characteristics are based on simulation. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125°C
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3.14.2 Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using
Equation1:
Equation 1TJ = TA + (PD x RθJA)
Where:
TA is the ambient temperature in °C.
RθJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal
power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O< PINT and may be neglected. On the other hand,
PI/O may be significant, if the device is configured to continuously drive external modules
and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
Equation 2PD = K / (TJ + 273 °C)
Therefore, solving equations 1 and 2:
Equation 3K = PD x (TA + 273 °C) + RθJA x PD2
Where:
K is a constant for the particular part, which may be determined from Equation3
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values
of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any
value of TA. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
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3.15 I/O pad electrical characteristics
3.15.1 I/O pad types
The device provides four main I/O pad types depending on the associated alternate
functions: Slow pads—These pads are the most common pads, providing a good compromise
between transition time and low electromagnetic emission. Medium pads—These pads provide transition fast enough for the serial communication
channels with controlled current to reduce electromagnetic emission. Fast pads—These pads provide maximum speed. There are used for improved Nexus
debugging capability. Input only pads—These pads are associated to ADC channels and the external 32 kHz
crystal oscillator (SXOSC) providing low input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance.
3.15.2 I/O input DC characteristics
Table 16 provides input DC electrical characteristics as described in Figure6.
Figure 6. I/O input DC electrical characteristics definition
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3.15.3 I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads: Table 17 provides weak pull figures. Both pull-up and pull-down resistances are
supported. Table 18 provides output driver characteristics for I/O pads when in SLOW
configuration. Table 19 provides output driver characteristics for I/O pads when in MEDIUM
configuration. Table 20 provides output driver characteristics for I/O pads when in FAST
configuration.
Table 16. I/O input DC electrical characteristics VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage.
Table 17. I/O pull-up/pull-down DC electrical characteristics
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VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified. The configuration PAD3V5= 1 when VDD=5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 17. I/O pull-up/pull-down DC electrical characteristics (continued)
Table 18. SLOW configuration output buffer electrical characteristics VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified The configuration PAD3V5= 1 when VDD=5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
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Table 19. MEDIUM configuration output buffer electrical characteristics VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified The configuration PAD3V5= 1 when VDD=5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 20. FAST configuration output buffer electrical characteristics
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3.15.4 Output pin transition times
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified The configuration PAD3V5= 1 when VDD=5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 20. FAST configuration output buffer electrical characteristics (continued)
Table 21. Output pin transition times VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
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3.15.5 I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in Table 22.
Table 23 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the IAVGSEG maximum value.
CL includes device and package capacitances (CPKG < 5 pF).
Table 22. I/O supply segment LBGA208 available only as development package for Nexus2+ All LQFP64 information is indicative and must be confirmed during silicon validation.
Table 23. I/O consumption
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Table 24 provides the weight of concurrent switching I/Os.
Due to the dynamic current limitations, the sum of the weight of concurrent switching I/Os on
a single segment must not exceed 100% to ensure device functionality.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to125 °C, unless otherwise specified Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Table 23. I/O consumption (continued)
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Table 24. I/O weight(1)
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Table 24. I/O weight(1) (continued)
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Table 24. I/O weight(1) (continued)
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Table 24. I/O weight(1) (continued)
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Table 24. I/O weight(1) (continued)
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Doc ID 14619 Rev 12 57/117 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to125 °C, unless otherwise specified All LQFP64 information is indicative and must be confirmed during silicon validation. SRC: “Slew Rate Control” bit in SIU_PCR
Table 24. I/O weight(1) (continued)
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3.16 RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
Figure 7. Start-up reset requirements
Figure 8. Noise filtering on reset signal
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Table 25. Reset electrical characteristics VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified This transient configuration does not occurs when device is used in the VDD = 3.3 V ± 10% range. CL includes device and package capacitance (CPKG<5 pF).
