SNJ54ABT16374AWD ,16-Bit Edge-Triggered D-type Flip-Flops With 3-State Outputs SN54ABT16374A, SN74ABT16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCBS205C – ..
SNJ54ABT16543WD ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS087C – FEBRUARY 1 ..
SNJ54ABT240J ,Octal Buffers/Drivers With 3-State Outputs SN54ABT240, SN74ABT240A OCTAL BUFFERS/DRIVERSWITH 3-STATE OUTPUTSSCBS098I – JANUARY 1991 – REVISED ..
SNJ54ABT240W ,Octal Buffers/Drivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SNJ54ABT244FK ,Octal Buffers Drivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SNJ54ABT244J ,Octal Buffers Drivers With 3-State Outputslogic diagram (positive logic)1 191OE 2OE218 11 91A1 1Y1 2A1 2Y1416 13 71A2 1Y2 2A2 2Y2614 15 51A3 ..
SPX29150U , 1.5A High Current Low Dropout Voltage Regulator Adjustable & Fixed Output, Fast Response
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SPX29151T5-1.8 , 1.5A Low Dropout Voltage Regulator Adjustable & Fixed Output, Fast Response Time
SPX29151U5-5.0 , 1.5A Low Dropout Voltage Regulator Adjustable & Fixed Output, Fast Response Time
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SNJ54ABT16374AWD
16-Bit Edge-Triggered D-type Flip-Flops With 3-State Outputs
MIL-STD-883, Method 3015 Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17 Typical V OLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up
and Power Down Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB
Layout High-Drive Outputs (–32-mA IOH , 64-mA IOL) Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
descriptionThe ’ABT16374A are 16-bit edge-triggered
D-type flip-flops with 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16374A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16374A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1Q2
GND
1Q3
1Q4CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1D2
GND
1D3
1D4CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
