SN75LVDS84DGGR ,FlatLink(TM) TransmitterSLLS270D–MARCH 1997–REVISED NOVEMBER 2007DESCRIPTION (CONTINUED)The SN75LVDS84 requires no external ..
SN75LVDS84DGGRG4 ,FlatLink(TM) Transmitter 48-TSSOP 0 to 70SLLS270D–MARCH 1997–REVISED NOVEMBER 2007D0CLKINCLKOUTNextCyclePrevious Cycle Current CycleD0–1 D6+ ..
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SN75LVDS84-SN75LVDS84DGG-SN75LVDS84DGGR-SN75LVDS84DGGRG4
FlatLink(TM) Transmitter
1FEATURESGND
VCC
D10
GND
D11
D12
D13
D14
GND
D15
D16
D17
VCC
D18
D19
GND
GND
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSVCC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKIN
D20
P0052-02NC - Not Connected
DESCRIPTIONSLLS270D–MARCH 1997–REVISED NOVEMBER 2007
www.ti.com
FLATLINK™ TRANSMITTERS
23• 21:3 Data
Million Suited
Transmission
Very Low 21 Data Low-Voltage
TTL and3 Data Channels Plus Clock-Out
Low-Voltage Differential Operates Supply and
250 mW (Typ) 5-V Tolerant Data Inputs ESD Protection SN75LVDS84
Edge-Triggered Inputs Packagedin Thin Shrink Small-Outline
Package Terminal Pitch Consumes Less Than1 mW When Disabled Wide Phase-Lock Input Frequency Range: 31 No External Components Required for PLL Outputs Meetor Exceed the Requirementsof
ANSI EIA/TIA-644 Improved DS90C561The SN75LVDS84 contains three 7-bit parallel-load serial-out shift registers,a 7× clock
synthesizer, differential signaling (LVDS) line driversina single integrated circuit. These
functions allow21 bitsof single-ended low-voltage TTL (LVTTL) datato be synchronously transmitted over three
balanced-pair conductors for receiptbya compatible receiver, suchas the SN75LVDS82or SN75LVDS86.
When transmitting, are each loaded into registersof the SN75LVDS84 on the falling edgeof
the input clock signal (CLKIN). The frequencyof CLKINis multiplied seven times and then usedto unload the
data registersin 7-bit slices and serially. The three serial streams anda phase-locked clock (CLKOUT) are then
outputto LVDS output drivers. The frequencyof CLKOUTis the sameas the input clock, CLKIN.
AVAILABLE OPTIONS(1)
LATCHING CLOCK EDGE
FALLINGSN75LVDS84DGG
SN75LVDS84DGGR
