SN75LVDS83ADGGR ,Flatlink 10-100MHz Transmitter 56-TSSOP -10 to 70 SLLS980E–JUNE 2009–REVISED NOVEMBER 20165 Description (continued)The SN75LVDS83A requires no exter ..
SN75LVDS83BDGG ,10-135 MHz 28-bit FlatLink? LVDS Transmitter/Serializer 56-TSSOP -10 to 70Features 2 Applications1• LVDS Display Series Interfaces Directly to LCD • LCD Display Panel Driver ..
SN75LVDS83BDGGR ,10-135 MHz 28-bit FlatLink? LVDS Transmitter/Serializer 56-TSSOP -10 to 70Thermal Characteristics table..... 10• Changed G7(LSB) to G7(MSB) in Figure 15... 21• Added Note C ..
SN75LVDS83BZQLR ,10-135 MHz 28-bit FlatLink? LVDS Transmitter/Serializer 56-BGA MICROSTAR JUNIOR -10 to 70Electrical Characteristics....... 713.1 Trademarks..... 327.7 Timing Requirements... 813.2 Electros ..
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SN75LVDS83ADGG-SN75LVDS83ADGGR
Flatlink 10-100MHz Transmitter 56-TSSOP -10 to 70
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SN75LVDS83ASLLS980E –JUNE 2009–REVISED NOVEMBER 2016
SN75LVDS83A Flatlink™ Transmitter Features LVDS Display SerDes Interfaces Directlyto LCD
Display Panels with Integrated LVDS Package Options: 8.1 mm×14 mm TSSOP 3.3-V Tolerant Data Inputs Transfer Rateupto 100 Mpps (Mega Pixel Per
Second) Pixel Clock Frequency Range:10 MHzto 100
MHz Suitedfor Display Resolutions Ranging From
HVGAupto HD With Low EMI Operates Froma Single 3.3-V Supply and
170 mW (Typical)at75 MHz 28 Data Channels Plus ClockIn Low-Voltage TTL4 Data Channels Plus Clock Out Low-Voltage
Differential Consumes Less Than1 mW When Disabled Selectable Risingor Falling Clock Edge Triggered
Inputs ESD: 5000V HBM Support Spread Spectrum Clocking (SSC) Compatible Withall OMAP™ 2x, OMAP™ 3x, and
DaVinci™ Application Processors
Applications Tablets Industrial PC, Laptop, and Other Factory
Automation Displays Patient Monitor and Medical Equipment Displays Electronic Point-of-Sale (EPOS) Displays Printer Displays
DescriptionThe SN75LVDS83A Flatlink™ transmitter device
contains four 7-bit parallel-load serial-out shift
registers,a 7× clock synthesizer, and five Low-
Voltage Differential Signaling (LVDS) line driversina
single integrated circuit. These functions allow28 bits single-ended LVTTL data to be synchronously
transmitted over five balanced-pair conductors for
receipt bya compatible receiver, such as the
SN75LVDS82 and LCD panels with integrated LVDS
receiver.
When transmitting, data bits D0 through D27 are
each loaded into registers upon the edgeof the input
clock signal (CLKIN). The risingor falling edgeof the
clock can be selected via the clock select (CLKSEL)
pin. The frequency of CLKINis multiplied seven
times, and then usedto unload the data registersin
7-bit slices and serially. The four serial streams anda
phase-locked clock (CLKOUT) are then output to
LVDS output drivers. The frequencyof CLKOUTis
the sameas the input clock, CLKIN.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
LVDS Application
