SN75LVDS82DGGR ,FlatLink(TM) ReceiverMaximum Ratings . 512 Layout.... 197.2 ESD Ratings........ 512.1 Layout Guidelines.... 197.3 Recomm ..
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SN75LVDS83ADGG ,Flatlink 10-100MHz Transmitter 56-TSSOP -10 to 70Electrical Characteristics....... 713.1 Receiving Notification of Documentation Updates 317.6 Dissi ..
SN75LVDS83ADGGR ,Flatlink 10-100MHz Transmitter 56-TSSOP -10 to 70 SLLS980E–JUNE 2009–REVISED NOVEMBER 20165 Description (continued)The SN75LVDS83A requires no exter ..
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SN75LVDS82-SN75LVDS82DGG-SN75LVDS82DGGR
FlatLink(TM) Receiver
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SN75LVDS82SLLS259J–NOVEMBER 1996–REVISED OCTOBER 2016
SN75LVDS82 FlatLink™ Receiver Features 4:28 Data Channel Expansionatupto
1904 Mbps Throughput Suitedfor SVGA, XGA,or SXGA Display
Data Transmission From Controllerto
Display With Very Low EMI Four Data Channels and Clock Low-Voltage
Differential ChannelsIn and28 Data and
Clock Low-Voltage TTL Channels Out Operates Froma Single 3.3-V Supply With
250 mW (Typical) 5-V Tolerant SHTDN Input Falling Clock-Edge-Triggered Outputs Packagedin Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal Pitch Consumes Less Than1 mW When Disabled Pixel Clock Frequency Rangeof31 MHzto MHz No External Components Required for PLL Inputs Meetor Exceed the Requirementsof
ANSI EIA/TIA-644 Standard
Applications Printers Appliances With an LCD Digital Cameras Laptop and PC Displays Industrial PC, Laptop,
and other Factory Automation Displays Patient
Monitor and Medical Equipment Displays
Projectors Weight Scales
DescriptionThe SN75LVDS82 FlatLink™ receiver contains four
serial-in, 7-bit parallel-out shift registers,a 7× clock
synthesizer, and five low-voltage differential signaling
(LVDS) line receiversina single integrated circuit.
These functions allow receipt of synchronous data
from a compatible transmitter, such as the
SN75LVDS83B, over five balanced-pair conductors,
and expansionto 28 bitsof single-ended low-voltage
TTL (LVTTL) synchronous dataata lower transfer
rate. The SN75LVDS82 can also be used with the
SN75LVDS84for 21-bit transfers.
When receiving, the high-speed LVDS data is
received and loaded into registers at the rate of
seven times (7×) the LVDS input clock (CLKIN). The
datais then unloadedtoa 28-bit-wide LVTTL parallel
busat the CLKIN rate.A phase-locked loop (PLL)
clock synthesizer circuit generatesa 7× clock for
internal clocking and an output clock for the
expanded data. The SN75LVDS82 presents valid
data on the falling edge of the output clock
(CLKOUT).
The SN75LVDS82 requires only five line-termination
resistors for the differential inputs and little or no
control. The data bus appears the sameat the input the transmitter and outputof the receiver with the
data transmission transparentto the user.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
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