SN74V3680-6PEU ,16384 x 36 Synchronous FIFO MemorySN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 × 36, 2048 × 36, 4096 × 36, 8 ..
SN74V3690-6PEU ,32768 x 36 Synchronous FIFO MemorySN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 × 36, 2048 × 36, 4096 × 36, 8 ..
SN75107A ,Dual Line Receiverlogic diagram (positive logic)6S11A2 41B 1Y51G82G12 92A 2Y112B2POST OFFICE BOX 655303 • DALLAS, TEX ..
SN75107AD ,Dual Line Receiver SN55107A, SN75107A, SN75107B, SN75108A DUAL LINE RECEIVERS SLLS069D – JANUARY 1977 – REVISED APRI ..
SN75107AD ,Dual Line Receivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, V (see ..
SN75107ADR ,Dual Line Receiver SN55107A, SN75107A, SN75107B, SN75108A DUAL LINE RECEIVERS SLLS069D – JANUARY 1977 – REVISED APRI ..
SPB04N50C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristics, at T =25°C unless otherwise specifiedjParameter Symbol Conditions Values Unitmin. ..
SPB04N60C2 ,for lowest Conduction Losses & fastest SwitchingFeatureProduct Summary• New revolutionary high voltage technologyV @ T650 VDS jmax• Ultra low gate ..
SPB04N60C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristics, at T =25°C unless otherwise specifiedjParameter Symbol Conditions Values Unitmin. ..
SPB04N60S5 ,for lowest Conduction LossesFeatureR 0.95 ΩDS(on)• New revolutionary high voltage technologyI 4.5 AD• Ultra low gate chargeP-TO ..
SPB07N60C2 ,for lowest Conduction Losses & fastest SwitchingFeatureProduct Summary• New revolutionary high voltage technologyV @ T650 VDS jmax• Ultra low gate ..
SPB07N60C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristics, at T =25°C unless otherwise specifiedjParameter Symbol Conditions Values Unitmin. ..
SN74V3680-6PEU
16384 x 36 Synchronous FIFO Memory
– SN74V3680 – 16384 × 36 Bit
– SN74V3690 – 32768 × 36 Bit 166-MHz Operation (6-ns Read/Write Cycle
Time) User-Selectable Input- and Output-Port Bus
Sizing
– ×36 in to ×36 out
– ×36 in to ×18 out
– ×36 in to ×9 out
– ×18 in to ×36 out
– ×9 in to ×36 out Big-Endian/Little-Endian User-Selectable
Byte Representation 5-V-Tolerant Inputs Fixed, Low, First-Word Latency Zero-Latency Retransmit Master Reset Clears Entire FIFO Partial Reset Clears Data, But Retains
Programmable Settings Selectable Synchronous/Asynchronous
Timing Modes for Almost-Empty and
Almost-Full Flags Program Programmable Flags by Either
Serial or Parallel Means Select Standard Timing (Using EF and FF
Flags) or First-Word Fall-Through (FWFT)
Timing (Using OR and IR Flags) Output Enable Puts Data Outputs in
High-Impedance State Easily Expandable in Depth and Width Independent Read and Write Clocks Permit
Reading and Writing Simultaneously High-Performance Submicron CMOS
Technology Available in 128-Pin Thin Quad Flat Pack
(TQFP)
descriptionThe SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally
deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible
bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits: Flexible ×36/×18/×9 bus matching on both read and write ports The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can
be read, is fixed and short. High-density offerings up to 1 Mbit
Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing,
telecommunications, data communications, and other applications that need to buffer large amounts of data
and match buses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or
9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus
matching (BM) during the master-reset cycle.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
