SN74V273-6PZA ,16384 x 18 Synchronous FIFO MemorySN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 183.3-V CMOS FIRS ..
SN74V273-6PZA ,16384 x 18 Synchronous FIFO MemorySN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 183.3-V CMOS FIRS ..
SN74V283-6PZA ,32768 x 18 Synchronous FIFO MemorySN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 183.3-V CMOS FIRS ..
SN74V293-6PZA ,65536 x 18 Synchronous FIFO MemorySN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 183.3-V CMOS FIRS ..
SN74V3680-6PEU ,16384 x 36 Synchronous FIFO MemorySN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 × 36, 2048 × 36, 4096 × 36, 8 ..
SN74V3690-6PEU ,32768 x 36 Synchronous FIFO MemorySN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 × 36, 2048 × 36, 4096 × 36, 8 ..
SPB02N60C3 ,for lowest Conduction Losses & fastest SwitchingFeatureR 3 ΩDS(on)• New revolutionary high voltage technologyI 1.8 AD• Ultra low gate chargeP-TO263 ..
SPB02N60S5 ,for lowest Conduction LossesCharacteristics, at Tj=25°C unless otherwise specifiedParameter Symbol Conditions Values Unitmin. t ..
SPB03N60C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristicsParameter Symbol Conditions Values Unitmin. typ. max.Transconductance g V ≥2*I *R , ..
SPB03N60S5 ,for lowest Conduction LossesCharacteristics, at Tj=25°C unless otherwise specifiedParameter Symbol Conditions Values Unitmin. t ..
SPB04N50C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristics, at T =25°C unless otherwise specifiedjParameter Symbol Conditions Values Unitmin. ..
SPB04N60C2 ,for lowest Conduction Losses & fastest SwitchingFeatureProduct Summary• New revolutionary high voltage technologyV @ T650 VDS jmax• Ultra low gate ..
SN74V273-6PZA
16384 x 18 Synchronous FIFO Memory
166-MHz Operation 6-ns Read/Write Cycle Time User-Selectable Input and Output Port BusSizing
– ×9 in to ×9 out
– ×9 in to ×18 out
– ×18 in to ×9 out
– ×18 in to ×18 out Big-Endian/Little-Endian User-Selectable
Byte Representation 5-V-Tolerant Inputs Fixed, Low First-Word Latency Zero-Latency Retransmit Master Reset Clears Entire FIFO Partial Reset Clears Data, but Retains
Programmable Settings Empty, Full, and Half-Full Flags Signal FIFO
Status
Almost-Full Flags Program Programmable Flags by Either
Serial or Parallel Means Select Standard Timing (Using EF and FF
Flags) or First-Word Fall-Through (FWFT)
Timing (Using OR and IR Flags) Output Enable Puts Data Outputs in
High-Impedance State Easily Expandable in Depth and Width Independent Read and Write Clocks Permit
Reading and Writing Simultaneously High-Performance Submicron CMOS
Technology Glueless Interface With ’C6x DSPs Available in 80-Pin Thin Quad Flat Pack
(TQFP) and 100-Pin Ball Grid Array (BGA)
Packages
descriptionThe SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in
first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.
There is flexible ×9/×18 bus matching on both read and write ports.
The period required by the retransmit operation is fixed and short.
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be
read, is fixed and short.
These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and
other applications that need to buffer large amounts of data and match buses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit
or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during
the master-reset cycle.
The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO
on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and
read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.
An output-enable (OE) input is provided for 3-state control of the outputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
