SN74SSTVF16859S8 ,13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74SSTVF16859SR ,13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs SCES429B − MARCH 2003 − ..
SN74TVC16222A ,22-Bit Voltage Clampelectrical characteristics; therefore, any one of them canbe used as the reference transistor. Beca ..
SN74TVC16222ADGGR ,22-Bit Voltage Clampelectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN74TVC16222ADGGR ,22-Bit Voltage Clamp SCDS087G − APRIL 1999 − REVISED APRIL 2005DGG, DGV, OR DL PACKAGE Membe ..
SN74TVC16222ADGVR ,22-Bit Voltage Clamp/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SPB02N60C3 ,for lowest Conduction Losses & fastest SwitchingFeatureR 3 ΩDS(on)• New revolutionary high voltage technologyI 1.8 AD• Ultra low gate chargeP-TO263 ..
SPB02N60S5 ,for lowest Conduction LossesCharacteristics, at Tj=25°C unless otherwise specifiedParameter Symbol Conditions Values Unitmin. t ..
SPB03N60C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristicsParameter Symbol Conditions Values Unitmin. typ. max.Transconductance g V ≥2*I *R , ..
SPB03N60S5 ,for lowest Conduction LossesCharacteristics, at Tj=25°C unless otherwise specifiedParameter Symbol Conditions Values Unitmin. t ..
SPB04N50C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristics, at T =25°C unless otherwise specifiedjParameter Symbol Conditions Values Unitmin. ..
SPB04N60C2 ,for lowest Conduction Losses & fastest SwitchingFeatureProduct Summary• New revolutionary high voltage technologyV @ T650 VDS jmax• Ultra low gate ..
SN74SSTVF16859-SN74SSTVF16859GR-SN74SSTVF16859GRG4-SN74SSTVF16859S8-SN74SSTVF16859SR
13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70
Package) Pinout and Functionality Compatible With
JEDEC Standard SSTV16859 600 ps Faster (Simultaneous Switching)
Than the JEDEC Standard SSTV16859 in
PC2700 DIMM Applications 1-to-2 Outputs to Support Stacked DDR
DIMMs Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line Outputs Meet SSTL_2 Class I
Specifications Supports SSTL_2 Data Inputs Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the
RESET Input RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low Pinout Optimizes DIMM PCB Layout Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering informationThis 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND DDQ
Q5B
Q4B
Q3B
Q2B
Q1B
D13
D12
VCC
VDDQ
GND
D11
D10
GND
RESET
GND
CLK
CLK
VDDQ
VCC REF
GND
GND DDQ
VCC
GND
VDDQ
