SN74SSTV32852GKFR ,24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74SSTV32852ZKFR ,24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and OutputsSN74SSTV32852 24-BIT TO 48-BIT REGISTERED BUFFERWITH SSTL_2 INPUTS AND OUTPUTSSCES361C – AUGUST 200 ..
SN74SSTVF16857 ,14-Bit Registered Buffer With SSTL_2 Inputs and Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74SSTVF16857GR ,14-Bit Registered Buffer With SSTL_2 Inputs and Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74SSTVF16859 ,13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74SSTVF16859GR ,13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputslogic diagram (positive logic)51RESET48CLK49CLK45VREFOne of 13 Channels35D1 16Q1A1DC132RQ1BTo 12 Ot ..
SPA20N60C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristicsParameter Symbol Conditions Values Unitmin. typ. max.Transconductance g V ≥2*I *R , ..
SPA20N65C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristics, at T =25°C unless otherwise specifiedjParameter Symbol Conditions Values Unitmin. ..
SPA21N50C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristicsParameter Symbol Values Unitmin. typ. max.R - - 0.6 K/WThermal resistance, junction ..
SPB02N60C3 ,for lowest Conduction Losses & fastest SwitchingFeatureR 3 ΩDS(on)• New revolutionary high voltage technologyI 1.8 AD• Ultra low gate chargeP-TO263 ..
SPB02N60S5 ,for lowest Conduction LossesCharacteristics, at Tj=25°C unless otherwise specifiedParameter Symbol Conditions Values Unitmin. t ..
SPB03N60C3 ,for lowest Conduction Losses & fastest SwitchingCharacteristicsParameter Symbol Conditions Values Unitmin. typ. max.Transconductance g V ≥2*I *R , ..
SN74SSTV32852GKFR-SN74SSTV32852ZKFR
24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs
Outputs Meet SSTL_2 Class IISpecifications Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the
RESET Input Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
description/ordering informationThis 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.
The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
