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SN74SSTUB32866ZKER
25-Bit Configurable Registered Buffer With Address-Parity Test
DESCRIPTION
SN74SSTUB32866SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
www.ti.com
25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST Pinout Optimizes DDR2 DIMM PCB Layout Control and RESET Inputs Configurableas 25-Bit 1:1or 14-Bit 1:2 •
Checks Parity on DIMM-Independent Data
Registered Buffer Inputs Chip-Select Inputs Gate the Data Outputs from •
Ableto Cascade witha Second
Changing State and Minimizes System Power SN74SSTUB32866
Consumption •
Supports Industrial Temperature Range Output Edge-Control Circuitry Minimizes (-40°Cto 85°C)
Switching Noisein an Unterminated LineThis 25-bit 1:1or 14-bit 1:2 configurable registered bufferis designed for 1.7-Vto 1.9-V VCC operation.In the
1:1 pinout configuration, only one device per DIMMis requiredto drive nine SDRAM loads.In the 1:2 pinout
configuration, two devices per DIMM are requiredto drive18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the
open-drain error (QERR) output.
The SN74SSTUB32866 operates froma differential clock (CLK and CLK). Data are registeredat the crossingof
CLK going high and CLK going low.
The SN74SSTUB32866 acceptsa parity bit from the memory controller on the parity bit (PAR_IN) input,
comparesit with the data received on the DIMM-independent D-inputs (D2–D3, D5–D6, D8–D25 when C0=0
and C1=0; D2–D3, D5–D6, D8–D14 when C0=0 and C1=1;or D1-D6, D8-D13 when C0=1 and C1=1) and
indicates whethera parity error has occurredon the open-drain QERR pin (active low). The conventionis even
parity; i.e., valid parityis defined as an even numberof ones across the DIMM-independent data inputs,
combined with the parity input bit. To calculate parity,all DIMM-independent data inputs mustbe tiedtoa known
logic state.
When usedasa single device, the C0 and C1 inputs are tied low.In this configuration, parityis checked on the
PAR_IN input signal, which arrives one cycle after the input datato whichit applies. Two clock cycles after the
data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.
When usedin pairs, the C0 inputof the first registeris tied low, and the C0 inputof the second registeris tied
high. The C1 inputof both registers are tied high. Parity, which arrives one cycle after the data inputto whichit
applies,is checkedon the PAR_IN input signalof the first device. Two clock cycles after the data are registered,
the corresponding PPO and QERR signals are generated on the second device. The PPO outputof the first
registeris cascaded to the PAR_IN of the second SN74SSTUB32866. The QERR output of the first
SN74SSTUB32866is left floating, and the valid error informationis latched on the QERR outputof the second
SN74SSTUB32866.
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKINGLFBGA–ZKE Tape and reel SN74SSTUB32866ZKER SB866
