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SN74SSTU32864CZKER
25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs
www.ti.com
FEATURES
DESCRIPTION/ORDERING INFORMATION
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTSSCES542B–JANUARY 2004–REVISED APRIL 2005
Differential Clock (CLK and CLK) Inputs Memberof the Texas Instruments Widebus+™ •
Supports LVCMOS Switching Levels on
Family Control and RESET Inputs Pinout Optimizes DDR2 DIMM PCB Layout •
RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces•
Configurableas 25-Bit 1:1or 14-Bit 1:2 All Outputs LowRegistered Buffer Latch-Up Performance Exceeds 100 mA Per•
Chip-Select Inputs Gate Data Outputs From
JESD 78, ClassIIChanging State and Minimize System Power
Consumption •
ESD Protection Exceeds JESD22This 25-bit 1:1or 14-bit 1:2 configurable registered bufferis designed for 1.7-Vto 1.9-VVCC operation.In the 1:1
pinout configuration, only one device per DIMMis requiredto drive nine SDRAMIn the 1:2 pinout
configuration, two devices per DIMM are requiredto drive18 SDRAM loads.
All inputs are SSTL_18, the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.
The SN74SSTU32864C operates froma differential clock (CLK and CLK). Data are registeredat the crossingof
CLK going high and CLK going low.
The C0 input controls the pinoutof the 1:2 pinout from register-A configuration (when low)to
register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low)to
14-bit 1:2 (when high). C0 and C1 should notbe switched during normal operation. They should be hard-wiredto valid lowor high levelto configure the registerin the desired mode.In the 25-bit 1:1 pinout configuration, the
A6, D6, and H6 terminals are driven low and should notbe used. the DDR2 RDIMM application, RESETis specifiedto be completely asynchronous with respectto CLK and
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the registeris
cleared and the data outputs are driven low quickly, relativeto the timeto disable the differential input receivers.
However, when coming outof reset, the register becomes active quickly, relativeto the time requiredto enable
the differential input receivers.As longas the data inputs are low, and the clockis stable during the time from the
low-to-high transitionof RESET until the input receivers fully enabled, the designof the SN74SSTU32864C
must ensure that the outputs remain low, thus ensuringno glitcheson the output. ensure defined outputs from the register beforea stable clock has been supplied, RESET mustbe heldin the
low state during power up.
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKINGLFBGA– GKE Tape and reel SN74SSTU32864CGKER S864C0°Cto 70°C LFBGA– ZKE Tape and reel SN74SSTU32864CZKER S864C Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelinesare availableat
