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SN74LVTH18514-SN74LVTH18514DGGR
3.3-V ABT Scan Test Devices With 20-Bit Universal Bus Transceivers
and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation
Down to 2.7 V UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors B-Port Outputs of ’LVTH182514 Devices
Have Equivalent 25-Ω Series Resistors, So
No External Resistors Are Required Compatible With the IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture SCOPE Instruction Set
– IEEE Std 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes Package Options Include 64-Pin Plastic
Thin Shrink Small-Outline (DGG) and 64-Pin
Ceramic Dual Flat (HKC) Packages Using
0.5-mm Center-to-Center Spacings
descriptionThe ’LVTH18514 and ’LVTH182514 scan test devices with 20-bit universal bus transceivers are members of
the TI SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990
boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GNDCC
GND
A10
A11
A12
A13
GND
A14
A15
A16
VCC
A17
A18
A19
GND
A20
CLKENAB
CLKAB
TDO
TMS
GNDCC
GND
B10
B11
B12
B13
GND
B14
B15
B16
VCC
B17
B18
B19
GND
B20
OEAB
LEAB
TDI
TCK
