SN74LVT8996PWR ,3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTSMULTIDROP-ADDRESSABLE IEEE STD 1149.1 ..
SN74LVTH125 ,3.3-V ABT Quadruple Bus Buffers With 3-State Outputslogic diagram (positive logic)1 101OE 3OE2 3 9 81A 1Y 3A 3Y4 132OE 4OE5 6 12 112A 2Y 4A 4YPin numbe ..
SN74LVTH125D ,3.3-V ABT Quadruple Bus Buffers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVTH125DBR ,3.3-V ABT Quadruple Bus Buffers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LVTH125DBRG4 , 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVTH125DBRG4 , 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SP707CP , Low Power Microprocessor Supervisory Circuits
SP707CP , Low Power Microprocessor Supervisory Circuits
SP707CP , Low Power Microprocessor Supervisory Circuits
SP707EN , Low Power Microprocessor Supervisory Circuits
SP707EN , Low Power Microprocessor Supervisory Circuits
SP707EN , Low Power Microprocessor Supervisory Circuits
SN74LVT8996DW-SN74LVT8996DWR-SN74LVT8996PW-SN74LVT8996PWR
3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver
Extend Scan Access From Board Level toHigher Levels of System Integration Promote Reuse of Lower-Level
(Chip/Board) Tests in System Environment While Powered at 3.3 V, Both the Primary
and Secondary TAPs Are Fully 5-V Tolerant
for Interfacing to 5-V and/or 3.3-V Masters
and Targets Switch-Based Architecture Allows Direct
Connect of Primary TAP to Secondary TAP Primary TAP Is Multidrop for Minimal Use of
Backplane Wiring Channels Shadow Protocols Can Occur in Any of
Test-Logic-Reset, Run-Test/Idle, Pause-DR,
and Pause-IR TAP States to Provide for
Board-to-Board Test and Built-In Self-Test
Primary-to-Secondary Connection Without
Use of Shadow Protocols Connect (CON) Pin Provides Indication of
Primary-to-Secondary Connection High-Drive Outputs (–32-mA IOH , 64-mA IOL)
Support Backplane Interface at Primary and
High Fanout at Secondary Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101) Package Options Include Plastic
Small-Outline (DW) and Thin Shrink
Small-Outline (PW) Packages, Ceramic
Chip Carriers (FK), and Ceramic DIPs (JT)
SN54LVT8996 ...JT PACKAGE
SN74LVT8996... DW OR PW PACKAGE
(TOP VIEW)BYP
GND
PTDO
PTCK
PTMS
PTDI
PTRST
CON
STDI
STCK
STMS
STDO
STRST
VCC
CON
STDI
STCK
BYP
GND
PTDO
PTCK
SN54LVT8996... FK PACKAGE
(TOP VIEW)A3A4
STRST
STDO
PTDI
PTRST A6A7A5
PTMS STMS
NC – No internal connection
descriptionThe ’LVT8996 10-bit addressable scan ports (ASP) are members of the T exas Instruments SCOPE testability
integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate
testing of complex circuit assemblies. Unlike most SCOPE devices, the ASP is not a boundary-scannable
device, rather, it applies TI’s addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test
access port (TAP) to extend scan access beyond the board level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
