SN74LVT8980ADWRG4 ,Embedded Test-Bus Controllers IEEE STD 1149.1 (JTAG) TAP Masters W/ 8-Bit Generic Host Interfaces 24-SOIC -40 to 85 ! ..
SN74LVT8980DW , EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SN74LVT8980DW , EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SN74LVT8986PM ,3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) Tap TransceiverFEATURES• Members of the Texas Instruments (TI) Family • Bypass (BYP –BYP ) Forces Primary to5 0of ..
SN74LVT8996DW ,3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTSMULTIDROP-ADDRESSABLE IEEE STD 1149.1 ..
SN74LVT8996DWR ,3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTSMULTIDROP-ADDRESSABLE IEEE STD 1149.1 ..
SP706TEU , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706TEU , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP707CP , Low Power Microprocessor Supervisory Circuits
SP707CP , Low Power Microprocessor Supervisory Circuits
SP707CP , Low Power Microprocessor Supervisory Circuits
SP707EN , Low Power Microprocessor Supervisory Circuits
SN74LVT8980ADW-SN74LVT8980ADWR-SN74LVT8980ADWRG4
Embedded Test-Bus Controllers IEEE STD 1149.1 (JTAG) TAP Masters W/ 8-Bit Generic Host Interfaces
Scan-Accessible Test/Maintenance
Facilities at Board and System Levels While Powered at 3.3 V, the TAP Interface Is
Fully 5-V Tolerant for Mastering Both 5-V
and/or 3.3-V IEEE Std 1149.1 Targets Simple Interface to Low-Cost 3.3-V
Microprocessors/Microcontrollers Via 8-Bit
Asynchronous Read/Write Data Bus Easy Programming Via Scan-Level
Command Set and Smart TAP Control Transparently Generate Protocols to
Support Multidrop TAP Configurations
Using TI’s Addressable Scan Port Flexible TCK Generator Provides
Programmable Division, Gated-TCK, and
Free-Running-TCK Modes Discrete TAP Control Mode Supports
Arbitrary TMS/TDI Sequences for
Noncompliant Targets Programmable 32-Bit Test Cycle Counter
Allows Virtually Unlimited Scan/Test Length Accommodate Target Retiming (Pipeline)
Delays of up to 15 TCK Cycles Test Output Enable (TOE) Allows for
External Control of TAP Signals High-Drive Outputs (−32-mA IOH , 64-mA IOL)
at TAP Support Backplane Interface and/or
High Fanout
descriptionThe ’LVT8980A embedded test-bus controllers (eTBCs) are members of the TI broad family of testability
integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of
complex circuit assemblies. Unlike most other devices of this family, the eTBCs are not boundary-scannable
devices; rather, their function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command
of an embedded host microprocessor/microcontroller. Thus, the eTBCs enable the practical and effective use
of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and
configuration/maintenance facilities at board and system levels.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
