SN74LVT573DWR ,3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputslogic diagram (positive logic)11OE ENOE11LE C111LE2 191D 1D 1Q3 18C1192D 2Q1Q4 1723D 3Q 1D 1D5 164D ..
SN74LVT574DBR ,3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LVT574DW ,3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputslogic diagram (positive logic)11OE ENOE11CLK C111CLK2 191D 1D 1Q3 18C1192D 2Q1Q4 1723D 3Q 1D 1D5 16 ..
SN74LVT574DWR ,3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State OutputsSN54LVT574, SN74LVT5743.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCBS139D ..
SN74LVT574PW , 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVT574PWR ,3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State OutputsSN54LVT574, SN74LVT5743.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCBS139D ..
SP706T , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706TCN , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706TCN , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706TCN , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706TCN , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706TCP , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SN74LVT573DBLE-SN74LVT573DW-SN74LVT573DWR
3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputs
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D − MAY 1992 − REVISED JULY 1995
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation
Down to 2.7 V Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF , R = 0) Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17 Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors Support Live Insertion Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
descriptionThese octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The eight latches of the ’LVT573 are transparent D-type latches. While the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect the internal operations of the latches.
Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT573 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT573 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LVT573 is characterized for operation from −40°C to 85°C.
GND
VCC
SN54LVT573 ...J OR W PACKAGE
SN74LVT573... DB, DW, OR PW PACKAGE
(TOP VIEW)21 2019
9101112131DOE7Q
GND
SN54LVT573... FK PACKAGE
(TOP VIEW)Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
