SN74LVT543DBLE ,3.3-V ABT Octal Registered Transceivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVT543DWR , 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT573DBLE ,3.3-V ABT Octal Transparent D-Type Latches With 3-State OutputsSN54LVT573, SN74LVT5733.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS138D − MAY ..
SN74LVT573DBR , 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVT573DW ,3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVT573DW ,3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SP706SEP , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706SEP , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706SEP , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706SEU , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706SEU , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SP706T , 3.0V/3.3V Low Power Microprocessor Supervisory Circuits
SN74LVT543-SN74LVT543DBLE
3.3-V ABT Octal Registered Transceivers With 3-State Outputs
Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation
Down to 2.7 V Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF , R = 0) Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17 Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors Support Live Insertion Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (JT) DIPs
descriptionThese octal transceivers are designed specifically
for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V
system environment.
The ’LVT543 contain two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate latch-enable (LEAB or LEBA)
and output-enable (OEAB or OEBA) inputs are
provided for each register to permit independent
control in either direction of data flow.
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,
LEBA, and OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
CEAB
GND
LEAB
OEAB
SN54LVT543... FK PACKAGE
(TOP VIEW)CEAB
GND
OEAB
LEABOEBALEBANC CEBAB1
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
