SN74LVT16543DGGR ,3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputs SCBS148C − MAY 1992 ..
SN74LVT16543DGGR ,3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVT16543DL ,3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVT16543DL ,3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputs SCBS148C − MAY 1992 ..
SN74LVT16646 ,3.3-V ABT 16-Bit Bus Transceivers and Registers With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LVT16646DL ,3.3-V ABT 16-Bit Bus Transceivers and Registers With 3-State Outputs SCBS149D ..
SP705CU , Low Power Microprocessor Supervisory Circuits
SP705CU , Low Power Microprocessor Supervisory Circuits
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SP706CP , Low Power Microprocessor Supervisory Circuits
SN74LVT16543-SN74LVT16543DGGR-SN74LVT16543DL
3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputs
Widebus Family Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation
Down to 2.7 V Typical V OLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF , R = 0) Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17 Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors Support Live Insertion Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes
PCB Layout Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
descriptionThe ’LVT16543 are 16-bit registered transceivers designed for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or
OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,
LEBA, and OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
