SN74LVT125D ,3.3-V ABT Quadruple Bus Buffers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LVT125DB , 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DBLE ,3.3-V ABT Quadruple Bus Buffers With 3-State Outputsfeatures independent line drivers with 3-state outputs. Each output is in the high-impedancestate w ..
SN74LVT125DBR ,3.3-V ABT Quadruple Bus Buffers With 3-State Outputs SCBS133F − MAY 1992 − REVISED OCTOBER 2003 ..
SN74LVT125DBRG4 ,3.3-V ABT Quadruple Bus Buffers With 3-State Outputs 14-SSOP -40 to 85maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVT125DR ,3.3-V ABT Quadruple Bus Buffers With 3-State Outputs SCBS133F − MAY 1992 − REVISED OCTOBER 2003 ..
SP691ACP , Low Power Microprocessor Supervisory with Battery Switch-Over
SP691ACP , Low Power Microprocessor Supervisory with Battery Switch-Over
SP691ACP , Low Power Microprocessor Supervisory with Battery Switch-Over
SP691ACT , Low Power Microprocessor Supervisory with Battery Switch-Over
SP691ACT , Low Power Microprocessor Supervisory with Battery Switch-Over
SP691ACT , Low Power Microprocessor Supervisory with Battery Switch-Over
SN74LVT125D-SN74LVT125DBLE-SN74LVT125DBR-SN74LVT125DBRG4-SN74LVT125DR-SN74LVT125DRG4-SN74LVT125PW-SN74LVT125PWR
3.3-V ABT Quadruple Bus Buffers With 3-State Outputs
Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 3.3 V, TA = 25°CIoff Supports Partial-Power-Down Mode
Operation Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
description/ordering informationThis bus buffer is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide
a TTL interface to a 5-V system environment.
The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance
state when the associated output-enable (OE) input is high.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
