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SN74LVCE161284DGGR-SN74LVCE161284DLR
19-Bit IEEE 1284 Translation Transceiver with Error-Free Power Up 48-SSOP 0 to 70
(TOP VIEW)A10
GND
VCC
PERI LOGIC IN
A14
A15
A16
A17
DIR
Y10
GND
VCC CABLE
PERI LOGIC OUT
C14
C15
C16
C17
HOST LOGIC IN
DESCRIPTION/ORDERING INFORMATION
SN74LVCE161284
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER Auto-Power-Up Feature Prevents Printer
Errors When PrinterIs Turned On, But No
Valid SignalIsat A9–A13 Pins 1.4-kΩ Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Insertion Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection±4
kV– Human-Body Model±8
kV– IEC 61000-4-2, Contact Discharge
(Connector Pins) ±15
kV– IEC 61000-4-2, Air-Gap Discharge
(Connector Pins) ±15
kV– Human-Body Model
(Connector Pins)The SN74LVCE161284is designed for 3-Vto 3.6-V VCC operation. This device provides asynchronous two-way
communication between data buses. The control-function implementation minimizes external
requirements.
This device has eight bidirectional bits; data can flowin the A-to-B direction when the direction-control input high andin the B-to-A direction when DIRis low. This device has five drivers that drive the cable side and
four receivers. The SN74LVCE161284 has one receiver dedicatedto the HOST LOGIC line anda driver
the PERI LOGIC line.
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKINGTube SN74LVCE161284DLSSOP–DL LVCE1612840°Cto 70°C Tape and reel SN74LVCE161284DLR
TSSOP– DGG Tape and reel SN74LVCE161284DGGR LVCE161284 drawings, standard packing quantities, thermal data, symbolization, PCB design guidelinesare availableat
