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SN74LVC74A-SN74LVC74AD-SN74LVC74ADBLE-SN74LVC74ADBR-SN74LVC74ADBRG4-SN74LVC74ADR-SN74LVC74ANSR-SN74LVC74APW-SN74LVC74APWLE-SN74LVC74APWR-SN74LVC74APWRG4-SN74LVC74ARGYR
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset
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SN54LVC74A, SN74LVC74ASCAS287U –JANUARY 1993–REVISED JANUARY 2017
SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset Features Operate From 1.65Vto 3.6V Inputs Accept Voltagesto 5.5V Maximumtpdof 5.2nsat 3.3V Typical VOLP (Output Ground Bounce)
<0.8Vat VCC= 3.3V,TA= 25°C Typical VOHV (Output VOH Undershoot)Vat VCC= 3.3V,TA= 25°C Latch-Up Performance Exceeds 250 mA Per
JESD17 ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 1000-V Charged-Device Model (C101)
Applications Servers Medical, Healthcare, and Fitness Telecom Infrastructures TVs, Set-Top Boxes, and Audio Test and Measurement Industrial Transport Wireless Infrastructure Enterprise Switching Motor Drives Factory Automation and Control
DescriptionThe SNx4LVC74A devices integrate two positive-
edge triggered D-type flip-flopsin one convenient
device.
The SN54LVC74Ais designed for 2.7-Vto 3.6-V VCC
operation, and the SN74LVC74A is designed for
1.65-Vto 3.6-V VCC operation. low levelat the preset (PRE)or clear (CLR) inputs
setsor resets the outputs, regardlessof the levelsof
the other inputs. When PRE and CLR are inactive
(high), dataat the data (D) input meeting the setup
time requirementsis transferredto the outputson the
positive-going edge of the clock pulse. Clock
triggering occursata voltage level andis not directly
relatedto the rise timeof the clock pulse. Following
the hold-time interval, dataat theD input can be
changed without affecting the levelsat the outputs.
The data I/Os and control inputs are overvoltage
tolerant. This feature allows the useof these devices
for down-translationina mixed-voltage environment.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram, Each Flip-Flop (Positive Logic)
