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SN74LVC574A-SN74LVC574ADBLE-SN74LVC574ADBR-SN74LVC574ADGVR-SN74LVC574ADW-SN74LVC574ADWR-SN74LVC574AGQNR-SN74LVC574ANSRG4-SN74LVC574APW-SN74LVC574APWR-SN74LVC574APWRG4-SN74LVC574ARGYR-SN74LVC574ARGYRG4-SN74LVC574AZQNR
Octal Edge-Triggered D-Type Flip-Flop With 3-State Outputs
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Specified From −40°C to 85°C,
−40°C to 125°C, and −55°C to 125°C Max tpd of 7 ns at 3.3 V Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC) Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds 250 mA Per
JESD 17 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LVC574A ...J OR W PACKAGE
SN74LVC574A... DB, DGV, DW, N, NS,
OR PW PACKAGE
(TOP VIEW)
SN54LVC574A... FK PACKAGE
(TOP VIEW)GND
VCC
CLK1 2019
9101112131DOE7Q
GND
CLK
SN74LVC574A... RGY PACKAGE
(TOP VIEW)120 11
CLK
GND
description/ordering informationThe SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
