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Partno	Mfg	Dc	Qty	Available	Descript
SN74LVC2G80DCUR	TI	N/a	400	avai	Dual Positive-Edge-Triggered D-Type Flip-Flop
SN74LVC2G80DCUR	TI ?	N/a	247	avai	Dual Positive-Edge-Triggered D-Type Flip-Flop
SN74LVC2G80YZPR	TI	N/a	3000	avai	Dual Positive-Edge-Triggered D-Type Flip-Flop

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SN74LVC2G80DCUR-SN74LVC2G80YZPR
Dual Positive-Edge-Triggered D-Type Flip-Flop
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW) VCC81CLK 71D 1Q 62Q 2D 5 2CLK
GND 54 2CLK6 2D2Q7 1Q1D VCC11CLK
SN74LVC2G80
This dual positive-edge-triggered D-type flip-flopis Availablein the Texas Instruments designed for 1.65-Vto 5.5-V VCC operation.NanoFree™ Package
When dataat the data (D) input meets the setup time• Supports 5-V VCC Operation requirement, the datais transferredto theQ output• Inputs Accept Voltagesto 5.5V on the positive-going edgeof the clock pulse. Clock• Max tpdof 4.2 nsat 3.3V triggering occursata voltage level andis not directly
relatedto the rise timeof the clock pulse. Following• Low Power Consumption, 10-μA Max ICC
the hold-time interval, dataat theD input can be• Typical VOLP (Output Ground Bounce) changed without affecting the levelsat the outputs.<0.8Vat VCC= 3.3V,TA= 25°C technology is a major• Typical VOHV (Output VOH Undershoot) concepts, using the die>2Vat VCC= 3.3V,TA= 25°C• Ioff Feature Supports Live Insertion, Partial- for partial-power-downPower-Down and Back Drive Protection Ioff circuitry disables theMode Operation current backflow• Latch-Up Performance Exceeds 100 mA through the device whenitis powered down.Per JESD 78, ClassII ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)