SN74LVC2G32DCUR ,Dual 2-Input Positive-OR GateLogic Diagram (Positive Logic)11A71Y21B52A32Y62B1An IMPORTANT NOTICE at the end of this data sheet ..
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SN74LVC2G32YZPR ,Dual 2-Input Positive-OR GateFeatures 3 DescriptionThis dual 2-input positive-OR gate is designed for1• Available in the Texas I ..
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SN74LVC2G32DCTR-SN74LVC2G32DCUR-SN74LVC2G32DCURE4-SN74LVC2G32DCURG4-SN74LVC2G32DCUT-SN74LVC2G32YZPR
Dual 2-Input Positive-OR Gate
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SN74LVC2G32SCES201N –APRIL 1999–REVISED SEPTEMBER 2015
SN74LVC2G32 Dual 2-Input Positive-OR Gate Features 3 DescriptionThis dual 2-input positive-OR gateis designed for Availablein the Texas Instruments 1.65-Vto 5.5-V VCC operation.NanoFree™ Package
The SN74LVC2G32 device performs the Boolean• Supports 5-V VCC Operation
function in positive logic.• Inputs Accept Voltagesto 5.5V Maximumtpdof 3.8nsat 3.3V NanoFree package technology is a major
breakthroughinIC packaging concepts, using the die• Low Power Consumption, 10-µA Maximum ICC as the package.• ±24-mA Output Driveat 3.3V
This deviceis fully specified for partial-power-down• Typical VOLP (Output Ground Bounce) applications using Ioff. The Ioff circuitry disables the<0.8Vat VCC= 3.3V,TA= 25°C outputs, preventing damaging current backflow• Typical VOHV (Output VOH Undershoot) through the device whenitis powered down.>2Vat VCC= 3.3V,TA= 25°C
Device Information(1)• Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection• Can Be Usedasa Down Translatorto Translate
Inputs Froma Maximumof 5.5V Downto the VCC
Level Latch-Up Performance Exceeds 100 mA Per (1) Forall available packages, see the orderable addendumatJESD 78, ClassII the endofthe data sheet. ESD Protection Exceeds JESD22 2000-V Human Body Model (A114-A) 1000-V Charged-Device Model (C101)
Applications Down Translation Logical OR
Logic Diagram (Positive Logic)
