SN74LVC2G132DCTR ,Dual 2-Input NAND Gate with Schmitt-Trigger InputsFEATURES DESCRIPTIONThis dual 2-input NAND gate with Schmitt-trigger2• Available in Texas Instrumen ..
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SP5659 , 2·7GHz I2C Bus Low Phase Noise Synthesiser
SP5659 , 2·7GHz I2C Bus Low Phase Noise Synthesiser
SP5659 , 2·7GHz I2C Bus Low Phase Noise Synthesiser
SP5659 , 2·7GHz I2C Bus Low Phase Noise Synthesiser
SP5659 , 2·7GHz I2C Bus Low Phase Noise Synthesiser
SP5659 , 2·7GHz I2C Bus Low Phase Noise Synthesiser
SN74LVC2G132DCTR-SN74LVC2G132DCUR
Dual 2-Input NAND Gate with Schmitt-Trigger Inputs 8-SM8 -40 to 125
DCT PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW) VCC81A 7 1Y 6 2B 5 2AGND 4 2A
GND 54 2A6 2B2Y7 1Y1B VCC11A
SN74LVC2G132This dual 2-input NAND gate with Schmitt-trigger
Availablein Texas Instruments NanoFree™ inputsis designed for 1.65-Vto 5.5-V VCC operation.
PackageThe SN74LVC2G132 contains two inverters and
• Supports 5-V VCC Operation performs the Boolean functionY=A⋅BorY=A+B
• Inputs Accept Voltagesto 5.5V in positive logic. The device functions as two
• Max tpdof 5.3 nsat 3.3V independent inverters, but becauseof Schmitt action, has different input threshold levels for positive-going
• Low Power Consumption, 10-μA Max ICC(VT+) and negative-going (VT-) signals.
• ±24-mA Output Driveat 3.3V technology is a major
• Typical VOLP (Output Ground Bounce) concepts, using the die
VCC= 3.3V, TA= 25°C• Typical VOHV (Output VOH Undershoot) from the slowestof input
VCC= 3.3V, TA= 25°C jitter-free output signals.
• Ioff Supports Live Insertion, Partial Power
Down Mode, and Back Drive Protection specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
• Support Translation Down (5Vto 3.3V and 3.3V outputs, preventing damaging current backflow
to 1.8V) through the device whenitis powered down.
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
