SN74LVC1G80DCKRG4 ,Single Positive-Edge-Triggered D-Type Flip-Flop 5-SC70 -40 to 125Maximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74LVC1G80YEAR ,Single Positive-Edge-Triggered D-Type Flip-FlopLogic Diagram (Positive Logic)2CCLKCC4TG QC C CC1D TG TG TGC C C(1) TG - Transmission Gate1An IMPOR ..
SN74LVC1G86DBVR ,Single 2-Input Exclusive-OR GateBlock DiagramEXCLUSIVE OR= 1Copyright 2017, Texas Instruments IncorporatedAn exclusive-OR gate has ..
SN74LVC1G86DBVRG4 ,Single 2-Input Exclusive-OR Gate 5-SOT-23 -40 to 125Features 3 DescriptionThe SN74LVC1G86 device performs the Boolean1• ESD Protection Exceeds JESD 22f ..
SN74LVC1G86DBVT ,Single 2-Input Exclusive-OR GateElectrical Characteristics....... 512.1 Receiving Notification of Documentation Updates 136.6 Switc ..
SN74LVC1G86DCKR ,Single 2-Input Exclusive-OR GateFeatures... 18.3 Feature Description...... 82 Applications..... 18.4 Function Table.... 93 Descript ..
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SN74LVC1G80DBVR-SN74LVC1G80DCKR-SN74LVC1G80DCKRG4-SN74LVC1G80YEAR
Single Positive-Edge-Triggered D-Type Flip-Flop
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SN74LVC1G80SCES221S –APRIL 1999–REVISED NOVEMBER 2016
SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop Features Availablein the Texas Instruments
NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltagesto 5.5V Supports Down Translationto VCC Maximumtpdof 4.2nsat 3.3V Low Power Consumption, 10-µA Maximum ICC ±24-mA Output Driveat 3.3V Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
Applications Test and Measurement Enterprise Switching Telecom Infrastructure Motor Drives
DescriptionThis single positive-edge-triggered D-type flip-flopis
designed for 1.65-Vto 5.5-V VCC operation.
When dataat the data (D) input meets the setup time
requirement, the datais transferredto theQ output the positive-going edgeof the clock pulse. Clock
triggering occursata voltage level andis not directly
relatedto the rise timeof the clock pulse. Following
the hold-time interval, dataat theD input can be
changed without affecting the levelat the output.
NanoFree™ package technology is a major
breakthroughinIC packaging concepts, using the die the package.
This deviceis fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device whenitis powered down.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
