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Home ›  SS74 > SN74LVC1G79DBVR-SN74LVC1G79DCKR-SN74LVC1G79DCKRG4-SN74LVC1G79DCKT-SN74LVC1G79YZPR,Single Positive-Edge-Triggered D-Type Flip-Flop
SN74LVC1G79DBVR-SN74LVC1G79DCKR-SN74LVC1G79DCKRG4-SN74LVC1G79DCKT-SN74LVC1G79YZPR Fast Delivery,Good Price
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Partno Mfg Dc Qty AvailableDescript
SN74LVC1G79DBVRTI N/a19642avaiSingle Positive-Edge-Triggered D-Type Flip-Flop
SN74LVC1G79DCKRTIN/a17940avaiSingle Positive-Edge-Triggered D-Type Flip-Flop
SN74LVC1G79DCKRG4TIN/a351avaiSingle Positive-Edge-Triggered D-Type Flip-Flop 5-SC70 -40 to 125
SN74LVC1G79DCKTTIN/a7228avaiSingle Positive-Edge-Triggered D-Type Flip-Flop
SN74LVC1G79YZPRTIN/a2930avaiSingle Positive-Edge-Triggered D-Type Flip-Flop


SN74LVC1G79DBVR ,Single Positive-Edge-Triggered D-Type Flip-FlopFeatures 3 DescriptionThe SN74LVC1G79 device is a single positive-edge-1• Available in the Texas In ..
SN74LVC1G79DCKR ,Single Positive-Edge-Triggered D-Type Flip-FlopBlock Diagram... 113 Description....... 18.3 Feature Description.... 114 Revision History........ 2 ..
SN74LVC1G79DCKRG4 ,Single Positive-Edge-Triggered D-Type Flip-Flop 5-SC70 -40 to 125Maximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74LVC1G79DCKT ,Single Positive-Edge-Triggered D-Type Flip-FlopElectrical Characteristics....... 611.2 Layout Example....... 146.6 Timing Requirements: T = –40°C ..
SN74LVC1G79YZPR ,Single Positive-Edge-Triggered D-Type Flip-FlopLogic Diagram (Positive Logic)2CCLK CC4TGQC C CC1D TG TG TGC C CCopyright 2017, Texas Instruments ..
SN74LVC1G80DBVR ,Single Positive-Edge-Triggered D-Type Flip-FlopFeatures 3 DescriptionThis single positive-edge-triggered D-type flip-flop is1• Available in the Te ..
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SN74LVC1G79DBVR-SN74LVC1G79DCKR-SN74LVC1G79DCKRG4-SN74LVC1G79DCKT-SN74LVC1G79YZPR
Single Positive-Edge-Triggered D-Type Flip-Flop
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SN74LVC1G79

SCES220U–APRIL 1999–REVISED APRIL 2017
SN74LVC1G79 Single Positive-Edge-Triggered D-Type Flip-Flop Features
Availablein the Texas Instruments
NanoFree™ Package Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) Supports 5-V VCC Operation Inputs Accept Voltagesto 5.5V Supports Down Translationto VCC Maxtpdof6nsat 3.3V and50 pF load Low Power Consumption, 10-µA Max ICC ±24-mA Output Driveat 3.3V Ioff supports Partial-Power-Down Mode and Back-
Drive Protection Applications Test and Measurement Enterprise Switching Telecom Infrastructure Personal Electronics White Goods Description
The SN74LVC1G79 deviceisa single positive-edge-
triggered D-type flip-flop thatis designedfor 1.65-Vto
5.5-V VCC operation.
When dataat the data (D) input meets the setup time
requirement, the datais transferredto theQ output the positive-going edgeof the clock pulse. Clock
triggering occursata voltage level andis not directly
relatedto the rise timeof the clock pulse. Following
the hold-time interval, dataat theD input can be
changed without affecting the levelat the output.
NanoFree™ package technology is a major
breakthroughinIC packaging concepts, using the die the package.
This deviceis fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the deviceis powered down. This
inhibits current backflow into the device which
prevents damageto the device.
Device Information(1)

(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
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