SN74LVC1G0832DCKR ,Single 3-Input Positive AND-OR GateFEATURES DESCRIPTIONThis device is designed for 1.65-V to 5.5-V VCC2• Available in the Texas Instru ..
SN74LVC1G08DBV , SINGLE 2-INPUT POSITIVE-AND GATE
SN74LVC1G08DBVR ,Single 2-Input Positive-AND GateFeatures 3 Description2This single 2-input positive-AND gate is designed for1• Available in the Ult ..
SN74LVC1G08DBVRG4 ,Single 2-Input Positive-AND Gate 5-SOT-23 -40 to 125Maximum Ratingsover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
SN74LVC1G08DBVT ,Single 2-Input Positive-AND GateBlock Diagram... 103 Description....... 18.3 Feature Description.... 104 Revision History........ 2 ..
SN74LVC1G08DBVT ,Single 2-Input Positive-AND GateFeatures 3 Description2This single 2-input positive-AND gate is designed for1• Available in the Ult ..
SP481ES , Low Power Half-Duplex RS-485 Transceivers
SP481ES , Low Power Half-Duplex RS-485 Transceivers
SP481REN , 1/10th Unit Load RS-485 Transceiver
SP481REN , 1/10th Unit Load RS-485 Transceiver
SP481REP , 1/10th Unit Load RS-485 Transceiver
SP483CS , Low Power Half-Duplex RS-485 Transceivers
SN74LVC1G0832DCKR
Single 3-Input Positive AND-OR Gate 6-SC70 -40 to 125
SN74LVC1G0832 www.ti.com SCES606D – SEPTEMBER 2004 – REVISED DECEMBER 2013 Single 3-Input Positive AND-OR Gate Check for Samples: SN74LVC1G0832 1FEATURES DESCRIPTION This device is designed for 1.65-V to 5.5-V V CC 2• Available in the Texas Instruments NanoFree™ operation. Package The SN74LVC1G0832 device is a single 3-input • Supports 5-V V Operation CC positive AND-OR gate. It performs the Boolean • Inputs Accept Voltages to 5.5 V function Y = (A • B ) + C in positive logic. • Provides Down Translation to V CC By tying one input to GND or V , the CC • Max t of 5 ns at 3.3 V pd SN74LVC1G0832 device offers two more functions. • Low Power Consumption, 10-µA Max I CC When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to V , • ±24-mA Output Drive at 3.3 V CC the device works as a 2−input OR gate (Y = B + C). • Input Hysteresis Allows Slow Input This device also works as a 2−input OR gate when B Transition and Better Switching Noise is tied to V (Y = A + C). CC Immunity at the Input NanoFree™ package technology is a major (V = 250 mV Typ @ 3.3 V) hys breakthrough in IC packaging concepts, using the die • Can Be Used in Three Combinations: as the package. – AND-OR Gate This device is fully specified for partial-power-down – AND Gate applications using I . The I circuitry disables the off off – OR Gate outputs, preventing damaging current backflow through the device when it is powered down. • I Supports Live Insertion, Partial-Power- off Down Mode, and Back-Drive Protection • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) YZP PACKAGE DCK PACKAGE DBV PACKAGE (TOP VIEW) (BOTTOM VIEW) (TOP VIEW) 3 4 B Y 1 6 C A C A 1 6 2 5 V GND CC 5 V GND 2 CC 1 6 C A 5 V GND 2 CC B 3 4 Y B 3 4 Y 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
