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SN74LVC112A-SN74LVC112ADBR-SN74LVC112ADGVR-SN74LVC112ADGVRG4-SN74LVC112ADR-SN74LVC112ANSR-SN74LVC112APW-SN74LVC112APWR
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
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SN74LVC112ASCAS289M –JANUARY 1993–REVISED DECEMBER 2014
SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop
With Clear And Preset Features 2 Applications Operates From 1.65Vto 3.6V • Servers Inputs Accept Voltagesto 5.5V • PCs Maxtpdof 4.8nsat 3.3V • Notebooks Typical VOLP (Output Ground Bounce) • Network switches 0.8Vat VCC= 3.3V,TA= 25°C • Toys Typical VOHV (Output VOH Undershoot) • I/O Expanders2Vat VCC= 3.3V,TA= 25°C • Electronic Pointsof Sale Latch-Up Performance Exceeds 250 mA Per
JESD17
3 Description ESD Protection Exceeds JESD22 This dual negative-edge-triggered J-K flip-flop is
designed for 1.65-Vto 3.6-V VCC operation.– 3000-V Human-Body Model 200-V Machine Model
Device Information(1) 1500-V Charged-Device Model
(1) Forall available packages, see the orderable addendumat
the endofthe datasheet.
Simplified Schematic
