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SN74LV8154MPWREP
Enhanced Product Dual 16-Bit Binary Counter With 3-State Output Registers 20-TSSOP -55 to 125
−55°C to 125°C Enhanced Diminishing Manufacturing
Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Can Be Used as Two 16 Bit Counters or a
Single 32 Bit Counter 2-V to 5.5-V VCC Operation Max tpd of 25 ns at 5 V (RCLK to Y) Typical VOLP (Output Ground Bounce)
<0.7 V at VCC = 5 V, TA = 25°C Typical VOHV (Output VOH Undershoot)
>4.4 V at VCC = 5 V, TA = 25°C Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds 250 mA Per
JESD 17standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description/ordering informationThe SN74LV8154 is a dual 16 bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC
operation.
This 16 bit counter (A or B) feeds a 16 bit storage register and each storage register is further divided into an
upper byte and lower byte. The GAL, GAU, GBL, and GBU inputs are used to select the byte that needs to be
output at Y0−Y7. CLKA is the clock for A counter and CLKB is the clock for B counter. RCLK is the clock for the
A and B storage registers. All three clock signals are positive-edge triggered.
A 32 bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.
To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied
to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability
of the driver.
This device is fully specified for partial-power-down applications using Ioff . The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION† For the most current package and ordering information, see the Package Option Addendum at the
end of this document, or see the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/packaging.
PW PACKAGE
(TOP VIEW)CLKA
CLKB
GAL
GAU
GBL
GBU
RCLK
RCOA
CLKBEN
GNDCC
CCLR
