SN74LV8151PW ,10-Bit Universal Schmitt-Trigger Buffers With 3-State Outputslogic diagram223PA322B N131T/C OE4D121Y1To Seven Other Channels2POST OFFICE BOX 655303 • DALLAS, TE ..
SN74LV8151PWR ,10-Bit Universal Schmitt-Trigger Buffers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV8151PWRG4 , 10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS
SN74LV8153PW ,Serial-To-Parallel Interfacemaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV8153PWR ,Serial-To-Parallel InterfaceFEATURES Single-Wire Serial Data InputThe SN74LV8153 is a serial-to-parallel data converter. Itacc ..
SN74LV8153PWR ,Serial-To-Parallel InterfaceSCLS555 − JUNE 2004data transmission protocol− The serial data should be sent as 2START-3ADDRESS-4 ..
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SN74LV8151PW-SN74LV8151PWR
10-Bit Universal Schmitt-Trigger Buffers With 3-State Outputs
Polarity Control for Y Outputs Selects Trueor Complementary Logic Typical V OLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C Typical V OHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°CIoff Supports Partial-Power-Down Mode
Operation Supports Mixed-Mode Voltage Operation on
All Ports Latch-Up Performance Exceeds 250 mA Per
JESD 17 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering informationThe SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V VCC
operation. The logic control (T/C) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs.
When T/C is high, the Y outputs are noninverted (true logic ), and when T/C is low, the Y outputs are inverted
(complementary logic).
When output-enable (OE) input is low, the device passes data from Dn to Yn. When OE is high, the Y outputs
are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple
Schmitt-trigger inverter.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
GND
