SN74LV74APW ,Dual Positive-Edge-Triggered D-Type Flip-FlopsMaximum Ratings.. 49.1 Application Information........ 126.2 ESD Ratings........ 49.2 Typical Appli ..
SN74LV74APWLE ,Dual Positive-Edge-Triggered D-Type Flip-FlopsSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54LV74A,SN74LV74AS ..
SN74LV74APWR ,Dual Positive-Edge-Triggered D-Type Flip-FlopsMaximum Ratings.. 49.1 Application Information........ 126.2 ESD Ratings........ 49.2 Typical Appli ..
SN74LV74APWRG4 ,Dual Positive-Edge-Triggered D-Type Flip-Flops 14-TSSOP -40 to 125Logic Diagram, Each Flip-Flop• ESD Protection Exceeds JESD 22(Positive Logic)– 2000-V Human-Body Mo ..
SN74LV74AQPWRQ1 ,Dual Positive-Edge-Triggered D-Type Flip-FlopsSN74LV74A-Q1DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPSCLS556B − DECEMBER 2003 − REVISED APRIL 2 ..
SN74LV74ARGYR ,Dual Positive-Edge-Triggered D-Type Flip-Flops SCLS381M–AUGUST 1997–REVISED MARCH 20155 Pin Configuration and FunctionsD, DGV, NS, or PW Package1 ..
SP3243EUCT-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EUCT-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EUCT-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EUCY , High Speed Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EUEA , High Speed Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EUEA-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SN74LV74A-SN74LV74AD-SN74LV74ADBR-SN74LV74ADR-SN74LV74ANSR-SN74LV74APW-SN74LV74APWLE-SN74LV74APWR-SN74LV74APWRG4-SN74LV74ARGYR
Dual Positive-Edge-Triggered D-Type Flip-Flops
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SN54LV74A, SN74LV74ASCLS381M –AUGUST 1997–REVISED MARCH 2015
SNx4LV74A Dual Positive-Edge-Triggered D-Type Flip-Flops Features 3 DescriptionThese dual positive-edge-triggered D-type flip-flops 2-Vto 5.5-V VCC Operation are designedfor 2-Vto 5.5-V VCC operation.• Maximumtpdof 8.5nsat5V Typical VOLP (Output Ground Bounce)
Device Information(1) 0.8Vat VCC= 3.3V,TA= 25°C Typical VOHV (Output VOH Undershoot) 2.3Vat VCC= 3.3V,TA= 25°C Support Mixed-Mode Voltage Operation
All Ports Ioff Supports Partial-Power-Down
Mode Operation (1) Forall available packages, see the orderable addendumat• Latch-up Performance Exceeds 250 mA the endofthe data sheet.
Per JESD17
Logic Diagram, Each Flip-Flop• ESD Protection Exceeds JESD22
(Positive Logic)– 2000-V Human-Body Model (A114-A) 500-V Charged-Device Model (C101)
Applications Programmable Logic Controller (PLC) DCS and PAC: Analog Input Module AV Receiver Server PSU STB, DVR, and Streaming Media (Withdraw) Server Motherboard
