SN74LV574ARGYR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State OutputsSN54LV574A, SN74LV574AOCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCLS412I − APRIL 19 ..
SN74LV594APW ,8-Bit Shift Registers With Output RegistersLogic Diagram (Positive Logic)• Independent Clocks for Shift and StorageRegisters• Latch-up Perform ..
SN74LV594APWG4 ,8-Bit Shift Registers With Output Registers 16-TSSOP -40 to 125Electrical Characteristics....... 611.1 Layout Guidelines.... 176.6 Switching Characteristics: V = ..
SN74LV594APWR ,8-Bit Shift Registers With Output Registers SCLS413J–APRIL 2005–REVISED MARCH 20155 Pin Configuration and FunctionsD, DB, or PW Package16-Pin ..
SN74LV594APWTG4 ,8-Bit Shift Registers With Output Registers 16-TSSOP -40 to 125Features 3 DescriptionThe SN74LV594A devices are 8-bit shift registers1• 2-V to 5.5-V V OperationCC ..
SN74LV595AD ,8-Bit Shift Registers With 3-State Output Registers SCLS414Q–APRIL 1998–REVISED APRIL 20165 Pin Configuration and FunctionsRGY Package TSSOP Package16 ..
SP3243EEA-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EEA-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EHCA , High Speed Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EHCA , High Speed Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EHCA , High Speed Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EHCA , High Speed Intelligent 3.0V to 5.5V RS-232 Transceivers
SN74LV574A-SN74LV574ADBR-SN74LV574ADGVR-SN74LV574ADW-SN74LV574APW-SN74LV574APWR-SN74LV574ARGYR
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
SN54LV574A, SN74LV574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS412I − APRIL 1998 − REVISED APRIL 2005
2-V to 5.5-V VCC Operation Max tpd of 10 ns at 5 V Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on
All Ports Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds 250 mA Per
JESD 17 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV574A... FK PACKAGE
(TOP VIEW)
SN54LV574A ...J OR W PACKAGE
SN74LV574A... DB, DGV, DW, NS,
OR PW PACKAGE
(TOP VIEW)GND
VCC
CLK12019
9101112131DOE7Q
GND
CLK
SN74LV574A... RGY PACKAGE
(TOP VIEW)120 11
CLK
GND
description/ordering information
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
