SN74LV374ATPWR ,SN74LV374AT 20-TSSOP -40 to 85features 3-state outputs designedspecifically for driving highly capacitive or relatively low-imped ..
SN74LV393ADBR ,Dual 4-Bit Binary Countersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV393ADR ,Dual 4-Bit Binary Counterslogic diagram, each counter (positive logic)CLR RQQACLK TRQQBTRQ QCTRQQDT2POST OFFICE BOX 655303 • ..
SN74LV393ANSR ,Dual 4-Bit Binary Counters/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LV393APW ,Dual 4-Bit Binary Countersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV393APWR ,Dual 4-Bit Binary Countersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
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SN74LV374ATPWR
SN74LV374AT 20-SO -40 to 85
DB, DW, NS, OR PW PACKAGE
(TOP VIEW)GND
VCC
CLK
RGY PACKAGE
(TOP VIEW) 20 11
CLK
GND
Inputs Are TTL-Voltage Compatible • Partial-Power-Down Mode• 4.5-Vto 5.5-V VCC Operation Performance Exceeds 250 mA Per• Typical tpdof 4.9 nsat5V• Typical VOLP (Output Ground Bounce) <0.8V Exceeds JESD22at VCC=5V,TA= 25°C Human-Body Model (A114-A)• Typical VOHV (Output VOH Undershoot) >2.3V Machine Model (A115-A)at VCC=5V,TA= 25°C Charged-Device Model (C101)• Support Mixed-Mode Voltage Operation on All
Ports
DESCRIPTION an octal edge-triggered D-type flip-flop. This device features 3-state outputs designedor relatively low-impedance loads. The deviceis particularly suitable for ports, bidirectional bus drivers, and working registers. clock theQ levels set upat the data (D)to place the eight outputsIn the high-impedance state, outputs state and the increased drive thetoof the latch. Old data can be retainedor new can state. during power upor power down, OE should througha pullupis determinedby the current-sinking capabilityof the driver. applications using Ioff. TheIoff circuitry disables the outputs,
