SN74LV32ATPWRQ1 ,Quadruple 2-Input Positive-OR Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV32D ,Quadruple 2-Input Positive-OR Gate 14-SOIC -40 to 85
SN74LV367ADBR ,Hex Buffers And Line Drivers With 3-State Outputs SCLS398G − APRIL 1998 − REVISED APRIL ..
SN74LV367ANSR ,Hex Buffers And Line Drivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV367ANSR ,Hex Buffers And Line Drivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV373 ,Octal Transparent D-Type Latch With 3-State Output 20-SSOP -40 to 85
SP3232EBEP , True 3.0V to 5.5V RS-232 Transceivers
SP3232EBEP , True 3.0V to 5.5V RS-232 Transceivers
SP3232EBEY , True 3.0V to 5.5V RS-232 Transceivers
SP3232EBEY , True 3.0V to 5.5V RS-232 Transceivers
SP3232ECA-L , True 3.0V to 5.5V RS-232 Transceivers
SP3232ECP , True 3.0V to 5.5V RS-232 Transceivers
SN74LV32ATPWRQ1
Quadruple 2-Input Positive-OR Gates
Max tpd of 6.5 ns at 5 V Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Voltage Operation on
All Ports Ioff Supports Partial-Power-Down Mode
Operation
description/ordering informationThese quadruple 2-input positive-OR gates are designed for 2-V to 5.5-V VCC operation.
The SN74LV32A performs the Boolean function Y�A� BorY�A• B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION† For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at http://www.ti.com. Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLE
(each gate)
logic diagram, each gate (positive logic) YGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
