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SN74LV27ADBRTIN/a87avaiTriple 3-Input Positive-NOR Gate
SN74LV27APWTIN/a7959avaiTriple 3-Input Positive-NOR Gate
SN74LV27APWTI&BBN/a4avaiTriple 3-Input Positive-NOR Gate
SN74LV27APWRTIN/a2000avaiTriple 3-Input Positive-NOR Gate


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SN74LV27ADBR-SN74LV27APW-SN74LV27APWR
Triple 3-Input Positive-NOR Gate
Typical VOHV (Output VOH Undershoot)>2.3 V at VCC = 3.3 V, TA = 25°CIoff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information

These triple 3-input positive-NOR gates are
designed for 2-V to 5.5-V VCC operation.
The ’LV27A devices perform the Boolean function
Y = A + B + C or Y = A • B • C in positive logic.
These devices are fully specified for
partial-power-down applications using Ioff . The Ioffcircuitry disables the outputs, preventing
damaging current backflow through the devices
when they are powered down.
ORDERING INFORMATION
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
SN54LV27A ...FK PACKAGE
(TOP VIEW)
1ANC3A1C
GND
NC − No internal connection
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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