SN74LV240APWR ,Octal Buffers/Drivers With 3-State OutputsLogic Diagram (Positive Logic)11OE2 181A1 1Y14 161A2 1Y26 141Y31A38 121A4 1Y4192OE11 92A1 2Y113 72A ..
SN74LV240PW , OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LV244A ,Octal Buffers/Drivers With 3-State OutputsSample & Support & ReferenceProduct Tools &TechnicalCommunityBuy DesignFolder Documents SoftwareSN7 ..
SN74LV244ADBR ,Octal Buffers/Drivers With 3-State OutputsMaximum Ratings . 410 Power Supply Recommendations... 136.2 ESD Ratings........ 411 Layout.... 136. ..
SN74LV244ADGVR ,Octal Buffers/Drivers With 3-State Outputs SCLS383N–SEPTEMBER 1997–REVISED OCTOBER 20155 Pin Configuration and FunctionsDB, DGV, DW, NS, PW P ..
SN74LV244ADW ,Octal Buffers/Drivers With 3-State OutputsMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SP3222EUCP , 3.3V, 1000 Kbps RS-232 Transceivers
SP3222EUCT , 3.3V, 1000 Kbps RS-232 Transceivers
SP3222EUCT , 3.3V, 1000 Kbps RS-232 Transceivers
SP3222EUCT , 3.3V, 1000 Kbps RS-232 Transceivers
SP3222EUCY , 3.3V, 1000 Kbps RS-232 Transceivers
SP3223EBCY , Intelligent 3.0V to 5.5V RS-232 Transceivers
SN74LV240ADBR-SN74LV240ADGVR-SN74LV240ANSR-SN74LV240APW-SN74LV240APWR
Octal Buffers/Drivers With 3-State Outputs
18 1Y11OE
1A1 16 1Y21A2 14 1Y31A3 12
1Y41A4 2Y1
2OE
2A1 7 2Y22A2Product
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SN54LV240A, SN74LV240ASCLS384I –SEPTEMBER 1997–REVISED FEBRUARY 2015
SNx4LV240A Octal Inverting Buffers/Drivers With 3-State Outputs Features 3 DescriptionThese octal buffers/drivers with inverted outputs are 2-Vto 5.5-V VCC Operation designed for 2-Vto 5.5-V VCC operation.• Maxtpdof 6.5nsat5V
The ’LV240A devices are designed specifically to• Typical VOLP (Output Ground Bounce) <0.8Vat improve both the performance and densityof 3-stateVCC= 3.3V,TA= 25°C memory address drivers, clock drivers, and bus-• Typical VOHV (Output VOH Undershoot) >2.3Vat oriented receivers and transmitters.VCC= 3.3V,TA= 25°C These devices are organized as two 4-bit buffers/line• Support Mixed-Mode Voltage Operationon All drivers with separate output-enable (OE) inputs.Ports When OEis low, the device passes inverted data Latch-Up Performance Exceeds 250 mA per from theA inputsto theY outputs. When OEis high,
the outputs arein the high-impedance state.JESD17 Ioff Supports Live Insertion, Partial Power-Down
Device Information(1)Mode, and Back Drive Protection• ESD Protection Exceeds JESD22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)– 1000-V Charged-Device Model (C101)
2 Applications(1) Forall available packages, see the orderable addendumat• Handset: Smartphone the endofthe data sheet. Network Switch Health and Fitness/ Wearables
Logic Diagram (Positive Logic)
