SN74LV165APWR ,Parallel-Load 8-Bit Shift RegistersLogic Diagram (Positive Logic)A B C D E F G H11 12 13 14 3 4 5 61SH/LD15CLKINH2CLK9S S S S S S S SQ ..
SN74LV165APWRG4 ,Parallel-Load 8-Bit Shift Registers 16-TSSOP -40 to 125Maximum Ratings.. 410 Power Supply Recommendations... 206.2 ESD Ratings........ 411 Layout.... 206. ..
SN74LV165APWRG4 ,Parallel-Load 8-Bit Shift Registers 16-TSSOP -40 to 125Logic Diagram (Positive Logic)A B C D E F G H11 12 13 14 3 4 5 61SH/LD15CLKINH2CLK9S S S S S S S SQ ..
SN74LV165APWTG4 , PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN74LV165ARGYR ,Parallel-Load 8-Bit Shift RegistersBlock Diagram... 152 Applications..... 18.3 Feature Description.... 163 Description....... 18.4 Dev ..
SN74LV165ARGYRG4 ,Parallel-Load 8-Bit Shift Registers 16-VQFN -40 to 125Maximum Ratings(1)seeMIN MAX UNITSupply voltage –0.5 7 V(2)Input voltage –0.5 7 V(2)Voltage range a ..
SP3222EBEY , True 3.0V to 5.5V RS-232 Transceivers
SP3222EBEY , True 3.0V to 5.5V RS-232 Transceivers
SP3222EEP , True 3.0V to 5.5V RS-232 Transceivers
SP3222EEP , True 3.0V to 5.5V RS-232 Transceivers
SP3222EHCY , 3.3V, 460 Kbps RS-232 Transceivers
SP3222EHCY , 3.3V, 460 Kbps RS-232 Transceivers
SN74LV165A-SN74LV165ADBR-SN74LV165ADG4-SN74LV165ADR-SN74LV165ADRG4-SN74LV165ANSR-SN74LV165APW-SN74LV165APWR-SN74LV165APWRG4-SN74LV165ARGYR-SN74LV165ARGYRG4
Parallel-Load 8-Bit Shift Registers
12 13 14 3 4 5 6 B C D E F G HSNx4LV165A Parallel-Load 8-Bit Shift Registers Features 2-Vto 5.5-V VCC Operation Maxtpdof 10.5nsat5V Support Mixed-Mode Voltage Operationon
All Ports Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds 250 mA Per
JESD17 ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
Applications IP Routers Enterprise Switches Access Control and Security: Access Keypads
and Biometrics Smart Meters: Power Line Communication
DescriptionThe ’LV165A devices are parallel-load, 8-bit shift
registers designed for 2-Vto 5.5-V VCC operation.
When the devices are clocked, datais shifted toward
the serial output QH. Parallel-in accessto each stage provided by eight individual direct data inputs that
are enabled bya low levelat the shift/load (SH/LD)
input. The ’LV165A devices featurea clock-inhibit
function and
Clockingis the clock
clock inhibit
CLK and CLK
CLK and
accomplishes
the high level inhibited
inputsto the
low, independently
SER.
These devices are fully specified for partial-power-
down applications using Ioff. TheIoff circuitry disables
the outputs, preventing damaging current backflow
through the devices when they are powered down.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
