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SN74LV161284DGGR-SN74LV161284DL
19-Bit Bus Interface
and IEEE Std 1284-II (Level-2 Type)
Electrical Specifications Flow-Through Architecture Optimizes PCB
Layout Latch-Up Performance Exceeds 250 mA Per
JEDEC 17 ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 300-V Machine Model (A115-A)
– 2000-V Charged-Device Model (C101)
description/ordering informationThe SN74LV161284 is designed for 4.5-V to
5.5-V VCC operation. This device provides
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
This device has eight bidirectional bits; data can
flow in the A-to-B direction when DIR is high, and
in the B-to-A direction when DIR is low. This
device also has five drivers, which drive the cable
side, and four receivers. The SN74LV161284 has
one receiver dedicated to the HOST LOGIC line
and a driver to drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y , and
PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low.
This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II
(level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT,
all cable-side pins have a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated
output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off,
PERI LOGIC OUT is set to low.
The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the
output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
A10
A11
A12
A13
VCC
GND
GND
VCC
PERI LOGIC IN
A14
A15
A16
A17
HOST LOGIC OUT
Y10
Y11
Y12
Y13
VCC CABLE
GND
GND
VCC CABLE
PERI LOGIC OUT
C14
C15
C16
C17
HOST LOGIC IN
