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SN74LV11ADGVRTIN/a169avaiTriple 3-Input Positive-AND Gates
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SN74LV11APWRTIN/a1674avaiTriple 3-Input Positive-AND Gates


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SN74LV11ADGVR-SN74LV11APW-SN74LV11APWR
Triple 3-Input Positive-AND Gates
Typical VOHV (Output VOH Undershoot)>2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information

These triple 3-input positive-AND gates are
designed for 2-V to 5.5-V VCC operation.
The ’LV11A devices perform the Boolean function�A•B• CorY�A�B� C in positive
logic.
These devices are fully specified for
partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing
damaging current backflow through the devices
when they are powered down.
ORDERING INFORMATION
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
SN54LV11A ...FK PACKAGE
(TOP VIEW)

GND1ANC3A1C
GND
NC − No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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