SN74LS374DW ,OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT/sc/package.2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265SN54LS373, SN54LS374, SN54S373, SN54S374, ..
SN74LS374DWR ,Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs/sc/package.2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265SN54LS373, SN54LS374, SN54S373, SN54S374, ..
SN74LS374DWR2 ,Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop WITH 3-STATE OUTPUT
SN74LS374DWR2 ,Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop WITH 3-STATE OUTPUT
SN74LS374J ,Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs/sc/package.2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265SN54LS373, SN54LS374, SN54S373, SN54S374, ..
SN74LS374N ,OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374OCTAL D-TYPE TRA ..
SP1481ECN , ±15kV Enhanced Low Power Half-Duplex RS-485 Transceivers
SP1481ECP , ±15kV Enhanced Low Power Half-Duplex RS-485 Transceivers
SP1485EMN , Enhanced Low Power Half-Duplex RS-485 Transceivers
SP1485EMN , Enhanced Low Power Half-Duplex RS-485 Transceivers
SP1491ECP , Full Duplex RS-485 Transceivers
SP1491EEN , Full Duplex RS-485 Transceivers
SN74LS374-SN74LS374DBR-SN74LS374DW-SN74LS374DWR-SN74LS374J-SN74LS374N
Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs
Buffered Control Inputs Clock-Enable Input Has Hysteresis toImprove Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data
Lines (’S373 and ’S374)
descriptionThese 8-bit registers feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The
high-impedance 3-state and increased
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system
without need for interface or pullup components.
These devices are particularly attractive for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are
transparent D-type latches, meaning that while
the enable (C or CLK) input is high, the Q outputs
follow the data (D) inputs. When C or CLK is taken
low, the output is latched at the level of the data
that was set up.
The eight flip-flops of the ’LS374 and ’S374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly.
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new
data can be entered, even while the outputs are off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . FK PACKAGE
(TOP VIEW)1QOC
GND
GND
VCC† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374. C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
