SN74LS374DWR2 ,Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop WITH 3-STATE OUTPUT
SN74LS374DWR2 ,Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop WITH 3-STATE OUTPUT
SN74LS374J ,Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs/sc/package.2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265SN54LS373, SN54LS374, SN54S373, SN54S374, ..
SN74LS374N ,OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374OCTAL D-TYPE TRA ..
SN74LS375NSR ,Quad bistable latches
SN74LS375NSR ,Quad bistable latches
SP1481ECN , ±15kV Enhanced Low Power Half-Duplex RS-485 Transceivers
SP1481ECP , ±15kV Enhanced Low Power Half-Duplex RS-485 Transceivers
SP1485EMN , Enhanced Low Power Half-Duplex RS-485 Transceivers
SP1485EMN , Enhanced Low Power Half-Duplex RS-485 Transceivers
SP1491ECP , Full Duplex RS-485 Transceivers
SP1491EEN , Full Duplex RS-485 Transceivers
SN74LS373DWR2-SN74LS373ML1-SN74LS374DWR2
Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop WITH 3-STATE OUTPUT
---------The SN74LS373 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appear transparent
to the data (data changes asynchronously) when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop
featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops. The SN74LS374 is
manufactured using advanced Low Power Schottky technology and is
compatible with all ON Semiconductor TTL families. Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
