SN74HSTL16918 ,9-Bit To 18-Bit HSTL-To-LVTTL Memory Address Latchmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HSTL16918DGGR ,9-Bit To 18-Bit HSTL-To-LVTTL Memory Address Latch SN74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED J ..
SN74LS00 ,Quad 2-Input NAND GateMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNIT(2) ..
SN74LS00D ,QUAD 2-INPUT NAND GATEBlock Diagram... 102 Applications..... 18.3 Feature Description.... 103 Description....... 18.4 Dev ..
SN74LS00D ,QUAD 2-INPUT NAND GATE
SN74LS00DBR ,Quad 2-input positive-NAND gatesLogic Diagram, Each Gate (Positive Logic)AYB1An IMPORTANT NOTICE at the end of this data sheet addr ..
SNJ54AHC541W ,Octal Buffers/Drivers With 3-State OutputsElectrical Characteristics....... 512 Device and Documentation Support........ 126.6 Switching Char ..
SNJ54AHCT04J ,Hex InvertersFeatures 3 DescriptionThe SNx4AHCT04 devices contain six independent1• Inputs are TTL-Voltage Compa ..
SNJ54AHCT08FK ,Quadruple 2-Input Positive-AND GatesFeatures 3 DescriptionThe SNx4AHCT08 devices are quadruple 2-input1• Inputs are TTL-Voltage Compati ..
SNJ54AHCT125J ,Quadruple Bus Buffer Gates With 3- State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SNJ54AHCT14J ,Hex Schmitt-trigger InvertersFeatures 3 DescriptionThe SNx4AHCT14 devices contain six independent1• Inputs are TTL-Voltage Compa ..
SNJ54AHCT240J ,Octal Buffers/Drivers With 3-State Outputs SCLS252N–OCTOBER 1995–REVISED FEBRUARY 20185 Pin Configuration and FunctionsSN54AHCT240, J or W Pa ..
SN74HSTL16918-SN74HSTL16918DGGR
9-Bit To 18-Bit HSTL-To-LVTTL Memory Address Latch
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per
JESD 17 Packaged in Plastic Thin Shrink
Small-Outline Package
descriptionThis 9-bit to 18-bit D-type latch is designed for
3.15-V to 3.45-V VCC operation. The D inputs
accept HSTL levels and the Q outputs provide
LVTTL levels.
The SN74HSTL16918 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of nine outputs is controlled with its
own latch-enable (LE) input.
Each of the nine D inputs is tied to the inputs of two
D-type latches that provide true data (Q) at the
outputs. While LE is low, the Q outputs of the
corresponding nine latches follow the D inputs.
When LE is taken high, the Q outputs are latched
at the levels set up at the D inputs.
The SN74HSTL16918 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE Output level before the
indicated steady-state input
conditions were established
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GNDCC
GND
1LE
GND REF
GND
2LE
GNDCC
GND
2Q9
1Q9
1Q2
2Q2
GND
1Q3
2Q3
VCC
1Q4
2Q4
GND
1Q5
2Q5
GND
1Q6
2Q6
VCC
1Q7
2Q7
GND
1Q8
2Q8CC
VCC
