SN74HCT574DWR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCT574DWRG4 ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SOIC -40 to 85maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCT574N ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HCT574NSR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT574PW ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT574PW ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs SCLS177E − MARCH 1984 − REVI ..
SNJ5438W ,Quadruple 2-Input Positive-NAND Buffers With Open-Collector Outp
SNJ5445J ,BCD-to-Decimal Decoders/Drivers
SNJ5450W ,Dual 2-Wide 2-Input AND-OR-invert Gates (One Gate Expandable)logic diagram (positive logic)1; 1x- 121X ( )2A 1AB 2Y2 1B20 1V2D "positive logic: Y = AB+ D ID(wit ..
SNJ5451J ,AND-OR-invert Gates
SNJ5451W ,AND-OR-invert Gates
SNJ5454J ,4-Wide AND-OR-invert GatesSDLS115SN5454. SN54LS54. SN7454. SN74LS§44-WIDE MliMWllll1lERT GATESDECEMBER 1983-REViSED MARCH 198 ..
SN74HCT574-SN74HCT574DBR-SN74HCT574DW-SN74HCT574DWG4-SN74HCT574DWR-SN74HCT574DWRG4-SN74HCT574N-SN74HCT574NSR-SN74HCT574PW-SN74HCT574PWG4-SN74HCT574PWR
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
Typical tpd = 22 ns ±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible Bus-Structured Pinoutdescription/ordering informationThese octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
bus driving. The ’HCT574 devices are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The eight flip-flops enter data on the low-to-high
transition of the clock (CLK) input.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without interface or pullup components.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.1D OE7Q1Q
GND
CLK
SN54HCT574... FK PACKAGE
(TOP VIEW)GND
CLK
