SN74HCT573NSR ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT573PW ,Octal Transparent D-Type Latches With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HCT573PWR ,Octal Transparent D-Type Latches With 3-State Outputslogic diagram (positive logic)1OE11LEC1191Q21D 1DTo Seven Other Channels†absolute
SN74HCT574 ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputslogic diagram (positive logic)1OE11CLKC1191Q21D 1DTo Seven Other Channels†absolute
SN74HCT574DBR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputslogic diagram (positive logic)1OE11CLKC1191Q21D 1DTo Seven Other Channels†absolute
SN74HCT574DW ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs SCLS177E − MARCH 1984 − REVI ..
SNJ54368AJ , HEX BUS DRIVERS WITH 3-STATE OUTPUTS
SNJ54368AJ , HEX BUS DRIVERS WITH 3-STATE OUTPUTS
SNJ5438W ,Quadruple 2-Input Positive-NAND Buffers With Open-Collector Outp
SNJ5445J ,BCD-to-Decimal Decoders/Drivers
SNJ5450W ,Dual 2-Wide 2-Input AND-OR-invert Gates (One Gate Expandable)logic diagram (positive logic)1; 1x- 121X ( )2A 1AB 2Y2 1B20 1V2D "positive logic: Y = AB+ D ID(wit ..
SNJ5451J ,AND-OR-invert Gates
SN74HCT573-SN74HCT573DBRG4-SN74HCT573DW-SN74HCT573DWR-SN74HCT573N-SN74HCT573NSR-SN74HCT573PW-SN74HCT573PWR
Octal Transparent D-Type Latches With 3-State Outputs
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Typical tpd = 21 ns ±6-mA Output Drive at 5 V
Low Input Current of 1 μA Max Inputs Are TTL-Voltage Compatible Bus-Structured Pinoutdescription/ordering informationThese octal transparent D-type latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. The ’HCT573 devices are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
While the latch-enable (LE) input is high, the
Q outputs respond to the data (D) inputs. When
LE is low, the outputs are latched to retain the data
that was set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased
drive provide the capability to drive bus lines without interface or pullup components.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.1D OE7Q1Q
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SN54HCT573... FK PACKAGE
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