SN74HCT138DR ,3-Line To 8-Line Decoders/Demultiplexersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT138DRG4 ,3-Line To 8-Line Decoders/Demultiplexers 16-SOIC -40 to 85/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HCT138N ,3-Line To 8-Line Decoders/Demultiplexerslogic diagram (positive logic)15Y01A14Y12B 13Y23 12C Y311Y410Y56G19Y64G2A7Y75G2BPin numbers shown a ..
SN74HCT138NSR ,3-Line To 8-Line Decoders/Demultiplexers SCLS171E − MARCH 1984 − REVISED SEPTEMBER ..
SN74HCT138NSR ,3-Line To 8-Line Decoders/Demultiplexersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCT138PW ,3-Line To 8-Line Decoders/Demultiplexersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SNF431BS , Programmable Voltage Reference
SNJ5400J ,Quadruple 2-Input Positive-NAND GatesLogic Diagram, Each Gate (Positive Logic)AYB1An IMPORTANT NOTICE at the end of this data sheet addr ..
SNJ5400W ,Quadruple 2-Input Positive-NAND GatesPin Functions (continued)PINI/O DESCRIPTIONCDIP, CFP, SOIC, SO CFPNAME LCCCPDIP, SO, SSOP (SN74xx00 ..
SNJ5401J ,Quadruple 2-Input Positive-NAND Gates With Open-Collector Output
SNJ5401J ,Quadruple 2-Input Positive-NAND Gates With Open-Collector Output
SNJ5402J ,Quadruple 2-Input Positive-NOR Gates
SN74HCT138-SN74HCT138D-SN74HCT138DR-SN74HCT138DRG4-SN74HCT138N-SN74HCT138NSR-SN74HCT138PW-SN74HCT138PWLE-SN74HCT138PWR
3-Line To 8-Line Decoders/Demultiplexers
±4-mA Output Drive at 5 V
Incorporate Three Enable Inputs to SimplifyCascading and/or Data ReceptionG2A
G2BANCY5Y0
GND
SN54HCT138 ...FK PACKAGE
(TOP VIEW)NC − No internal connection
G2A
G2B
GND
VCC
SN54HCT138 ...J OR W PACKAGE
SN74HCT138... D, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering informationThe ’HCT138 devices are designed for high-performance memory-decoding or data-routing applications
requiring very short propagation delay times. In high-performance memory systems, these decoders can
minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable
circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical
access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
