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SN74HC646DWR
Octal Bus Transceivers And Registers With 3-State Outputs
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Typical tpd = 11 ns True Data PathsSN54HC646 ...JT OR W PACKAGE
SN74HC646... DW OR NT PACKAGE
(TOP VIEW)
SN54HC646... FK PACKAGE
(TOP VIEW)CLKAB
SAB
DIR
GND
VCC
CLKBA
SBA
DIRSABCLKABB7A8
GND CLKBASBAV B6
NC – No internal connection
description/ordering informationThe ’HC646 devices consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers.
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the ’HC646 devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port may be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data may be
stored in one register and/or B data may be stored in the other register.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
