SN74HC374DWR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HC374N ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HC374NSR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HC374PWLE ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HC374PWR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HC377 ,Octal D-Type Flip-Flops With Clock Enablemaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN761633RTAR ,FM stereo radio with transmitter 40-WQFN -20 to 85
SN761633RTAR ,FM stereo radio with transmitter 40-WQFN -20 to 85
SN761634RTWR ,FM Transmitter 24-WQFN -20 to 85
SN761640 ,Digital TV Tuner IC 44-TSSOP -20 to 85
SN761640DBTR ,Digital TV Tuner IC 44-TSSOP -20 to 85
SN761640DBTR ,Digital TV Tuner IC 44-TSSOP -20 to 85
SN74HC374-SN74HC374DBR-SN74HC374DW-SN74HC374DWR-SN74HC374N-SN74HC374NSR-SN74HC374PWLE-SN74HC374PWR
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
Full Parallel Access for Loading1QOE5D8QGND
CLK
SN54HC374 ...FK PACKAGE
(TOP VIEW)
SN54HC374 ...J OR W PACKAGE
SN74HC374... DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)GNDCC
CLK
description/ordering informationThese 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ’HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
