SN74GTLP22033DGGR ,8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver with Split LVTTL Port and Feedback Path 48-TSSOP -40 to 85SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVERWITH SPLIT LVTTL PORT ..
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SN74GTLP22033DGGR
8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver with Split LVTTL Port and Feedback Path 48-TSSOP -40 to 85
and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring AO Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Open-Drain Outputs
(100 mA) Reduced LVTTL Outputs (–12 mA/12 mA) Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads Ioff , Power-Up 3-State, and BIAS VCCSupport Live Insertion Distributed VCC and GND Pins Minimize
High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
descriptionThe SN74GTLP22033 is a high-drive, 8-bit, three-wire registered transceiver that provides inverted
LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and
flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback
path for control and diagnostics monitoring, the same functionality as the SN74FB2033. The device provides
a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result
of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC
circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have
been designed and tested using several backplane models. The high drive allows incident-wave switching in
heavily loaded backplanes with equivalent load impedance down to 11 Ω.
The AO outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
AO1
GND
AI2
AO2
VCC
AI3
AO3
GND
AI4
AO4
AO5
AI5
GND
AO6
AI6
VCC
AO7
AI7
GND
AO8
AI8
OMODE0
GND
OEAB
ERC
OEAB
GND
CLKAB/LEAB
CLKBA/LEBA
GND
OEBA
VCC
LOOPBACK
GND
VREF
OMODE1
