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SN74GTLP1395PWR
Two 1-Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity
www.ti.com
FEATURES
DESCRIPTION/ORDERING INFORMATION
SN74GTLP1395TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERSWITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C–JUNE 2001–REVISED JANUARY 2006 ESD Protection Exceeds JESD22 TI-OPC™ Circuitry Limits Ringing on – 2000-V Human-Body Model (A114-A)Unevenly Loaded Backplanes – 200-V Machine Model (A115-A) OEC™ Circuitry Improves Signal Integrity and – 1000-V Charged-Device Model (C101)Reduces Electromagnetic Interference Bidirectional Interface Between GTLP SignalLevels and LVTTL Logic Levels Split LVTTL Port Providesa Feedback Pathfor Control and Diagnostics Monitoring LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Outputs (100 mA) LVTTL Outputs (–24 mA/24 mA) Variable Edge-Rate Control (ERC) InputSelects GTLP Rise and Fall Times for OptimalData-Transfer Rate and Signal IntegrityinDistributed Loads Ioff, Power-Up 3-State, and BIASVCC SupportLive Insertion Polarity Control Selects TrueorComplementary Outputs Latch-Up Performance Exceeds 100 mA PerJESD 78, ClassIIThe SN74GTLP1395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP andGTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that requireindividual output-enable and true/complement controls. The device allows for transparent and invertedtransparent modesof data transfer with separate LVTTL input and LVTTL output pins, which providea feedbackpath for control and diagnostics monitoring. The device providesa high-speed interface between cards operatingat LVTTL logic levels anda backplane operatingat GTLP signal levels andis designed especiallyto work withthe Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster thanstandard LVTTLor TTL) backplane operationisa direct resultof GTLP reduced output swing (<1 V), reducedinput threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OECand TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplanemodels. The high drive allows incident-wave switchingin heavily loaded backplanes, with equivalent loadimpedance downto11Ω.
GTLPis the Texas Instruments derivativeof the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.Theac specificationof the SN74GTLP1395is given onlyat the preferred higher noise margin GTLP, but the userhas the flexibilityof using this deviceat either GTL (VTT =1.2 Vand VREF= 0.8V)or GTLP (VTT =1.5 VandVREF=1V) signal levels. For information on using GTLP devicesin FB+/BTL applications, refertoTI applicationreports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLPin BTLApplications, literature number SCEA017.
Normally, theB port operatesat GTLP signal levels. The A-port and control inputs operateat LVTTL logic levels,but are 5-V tolerant and are compatible with TTLor 5-V CMOS devices. VREFis the B-port differential inputreference voltage.
Pleasebe aware thatan important notice concerning availability, standard warranty, and usein critical applicationsof Texas
